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The design of today's systems on chip (SoC's) raises difficult issues, in particular regarding verification. In their early design phases, hardware/software embedded systems are commonly described as ESL (Electronic System Level) models, such that their functional and transactional behavior can be analyzed by simulation. To enhance this validation process, we have previously developed a framework...
SoC design trends show increasing integration of special-purpose, third-party hardware blocks to accelerate diverse types of computation. These accelerator blocks interact with each other in unexpected ways when integrated into a complex, accelerator-rich SoC. In this work we propose a novel solution that guides verification engineers to the high-priority accelerator interaction scenarios during RTL...
The paper concerns a risk assessment and management methodology in critical infrastructures. The research objective is to adapt a ready-made risk manager, supporting information security- and business continuity management systems, to a new domain of application - critical infrastructure protection. First, a review of security issues in critical infrastructures was performed, with special focus on...
Keccak is the hash function selected by NIST as the new SHA-3 standard. Keccak is built on Sponge construction and it provides a new MAC function called MAC-Keccak. These new algorithms have raised questions with regards to side-channel leakage and analysis attacks of MAC-Keccak. So far there exists prior work on attacks of software implementations of MAC-Keccak, but there has been no comprehensive...
In a software development life cycle, system requirement management is an important but neglected step. A good requirement management can not only help developers to meet the requirements of the system, but also play an essential role for the communication among the stakeholders. Usually, natural language is used to describe and record the user requirements, yet it tends toward the situation of ambiguity,...
As technology scales, the hardware reliability challenge affects a broad computing market, rendering traditional redundancy based solutions too expensive. Software anomaly based hardware error detection has emerged as a low cost reliability solution, but suffers from Silent Data Corruptions (SDCs). It is crucial to accurately evaluate SDC rates and identify SDC producing software locations to develop...
In this paper, we present SADA, a static analysis tool to verify device drivers for TinyOS applications. Its broad goal is to certify that the execution paths of the application complies with a given hardware specification. SADA can handle a broad spectrum of hardware specifications, ranging from simple assertions about the values of configuration registers, to complex behaviors of possibly several...
Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of the system, or ensuring controlled occurrence of errors to perform approximate computing. In this paper, we are interested in characterization of error behavior at the level of instructions...
This paper presents a new method, capable of automatically generating attacks on binary programs from software crashes. We analyze software crashes with a symbolic failure model by performing concolic executions following the failure directed paths, using a whole system environment model and concrete address mapped symbolic memory in . We propose a new selective symbolic input method...
In modern computer architecture, memory is an indispensable medium that software and systems relies upon when running on the computer. Messages about memory access could reflect attributes of programs, which should be invaluable with decompilation and security-related fields. This paper presents a novel memory access algorithm-SEA (Static Execution Analysis) for analyzing stripped executables. In...
This paper presents a hybrid cache analysis for the simulation-based evaluation of data caches in embedded systems. The proposed technique uses static analyses at the machine code level to obtain information about the control flow of a program and the memory accesses contained in it. Using the result of these analyses, a high-speed source-level simulation model is generated from the source code of...
The design of embedded systems is often subject to strict requirements concerning various aspects, including real-time performance, power consumption and die area. For mobile devices especially, power consumption is often the most important issue. In order to meet these requirements an adequate system architecture needs to be designed and the embedded software needs to be optimized. For complex applications,...
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
Since low flexibility and non-dynamic problems exit in the process of software system integration, a multi-agent system frame model which introduces the agent techniques into system integration domain is proposed for problem solving. Based on the MAS frame model, independent software units are wrapped to agents, and their integration logic is described by the script language. Through explaining the...
Formal executable specification is one in the ITRS 2007 design report proposed solution to handle future design challenges. Specifications have to be checked for completeness and consistence. Furthermore, it is desirable to support later design steps by generating descriptions for simulation and synthesis, properties for simulative and formal verification and testing scripts. This can be achieved...
Programming embedded system software typically involves more than one programming language. Normally, a high-level language such as C/C++ is used for application oriented tasks and a low-level assembly language for direct interaction with the underlying hardware. In most cases those languages are closely interwoven and the assembly is embedded in the C/C++ code. Verification of such programs requires...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
The paper addresses the problem of creating a comprehensive fault injection environment, which integrates and improves various simulation and supplementary functions. This is illustrated with experimental results.
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