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HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary translation and applies aggressive optimizations through exploiting the runtime application behavior, these hybrid architectures provide better performance/watt. However, a poorly...
While high performance computing (HPC) is flourishing these years, the lack of HPC applications is increasingly serious. Conventional binary translation focused on desktop applications and embedded software, which could not be scaled up to HPC. This paper proposed a novel static binary translator MPI-QEMU aiming at MPI programs, the most commonly used on HPC platforms. Firstly, the efficient dynamic...
ISA-level fault injection, i.e. the injection of bit-flip faults in Instruction Set Architecture (ISA) registers and main memory words, is widely used for studying the impact of transient and intermittent hardware faults in computer systems. This paper compares two techniques for ISA-level fault injection: inject-on-read, and inject-on-write. The first technique injects bit-flips in a data-item (the...
Hardware errors are becoming more prominent with reducing feature sizes, however tolerating them exclusively in hardware is expensive. Researchers have explored software-based techniques for building error resilient applications for hardware faults. However, software based error resilience techniques need configurable and accurate fault injection techniques to evaluate their effectiveness. In this...
Traditional microprocessors have long benefited from the transistor density gains of Moore's law. Diminishing transistor speeds and practical energy limits however have created new challenges in technology, where the exponential performance improvements we have been accustomed to from previous computing generations continue to slowly cease. These factors signify that while transistors continue to...
This paper presents an extensive performance study of the implementation of Hardware Transactional Memory (HTM) in the Haswell generation of Intel x86 core processors. This study evaluates the strengths and weaknesses of this new architecture exploring several dimensions in the space of Transactional Memory (TM) application characteristics using the Eigenbench [1] and the CLOMP-TM [2] benchmarks....
A 64-bit RISC processor is designed for large applications that need large memory address. Due to the restriction of the instruction fixed length, loading a 64-bit address needs a number of instructions, leading to a penalty both of memory performance and memory consumption. This paper describes an address computation method based on hardware and software co-design. In our extended MIPS processor...
Hardware errors are on the rise with reducing feature sizes, however tolerating them in hardware is expensive. Researchers have explored software-based techniques for building error resilient applications. Many of these techniques leverage application-specific resilience characteristics to keep overheads low. Understanding application-specific resilience characteristics requires software fault-injection...
This paper presents FITIn, a bit-error injection tool designed for evaluating software-implemented hardware fault tolerance (SIHFT) mechanisms. Like most bit-error injection tools, FITIn injects faults at run time into the binary of a program. Unlike previous bit-error injection tools, FITIn allows a software developer to control the targets of injection campaigns at the level of a higher programming...
In these days, every new added hardware feature must not change the underlying instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing code. Nevertheless, this need for compatibility imposes a great number of restrictions to the designers, because it keeps them tied to a specific ISA and all its legacy hardware issues. Considering that the market is mainly dominated...
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative optimization. As we move to a multicore hybrid design, fine grained conflicts for shared data can violate the atomicity requirement of these blocks and lead to expensive squashes and rollbacks. However, as these atomic regions...
Due to device miniaturization and reducing supply voltage, embedded systems are becoming more susceptible to transient faults. Specifically, faults in control flow can change the execution sequence, which might be catastrophic for safety critical applications. Many techniques are devised using software, hardware or software-hardware co-design for control flow error checking. Software techniques suffer...
In the computer hardware industry, there are currently two highly successful instruction set architectures (ISAs): the CISC x86 ISA which is an established standard architecture in the personal computer and server markets, and the RISC ARM ISA which has become the standard in the fast growing ultra-mobile computing devices market, such as smart-phones and tablets. Program binaries that run on one...
Leakage power is an important concern in modern electronic designs. To efficiently employ power gating for leakage reduction in embedded processors, the architecture must provide a clear-cut software support for power gating and the power-gated unit must have significant idle times during the execution of the applications. We introduce power gating of individual datapath units for the embedded architecture...
Contention management is an important design component to a transactional memory system. Without effective contention management to ensure forward progress, a transactional memory system can experience live-lock, which is difficult to debug in parallel programs. Early work in contention management focused on heuristic managers that reacted to conflicts between transactions by picking the most appropriate...
Assessing and improving the level of system robustness with respect to soft errors has become one of the main design challenges, especially when designing critical embedded systems. In systems using microprocessors (e.g. most of SoCs) the system dependability is strongly correlated with the variable lifetimes. In this paper, we discuss the impact of compilation optimizations on the lifetimes in both...
This paper presents a significantly improved strategy for accelerating the method calls in the REALJava coprocessor. The hardware assisted virtual machine architecture is described shortly to provide context for the method call acceleration. The strategy is implemented in an FPGA prototype. It allows measurements of real life performance increase, and validates the whole co-processor concept. The...
As a key part of reverse engineering, decompilation plays a very important role in software security and maintenance. Unfortunately, most existing decompilation tools suffer from the low accuracy in identifying variables, functions and composite structures, which results in poor readability. To address these limitations, we present a practical decompiler called C-Decompiler for Windows C programs...
This paper presents an efficient software technique to detect and correct control-flow errors through addition of redundant codes in a given program. The key innovation performed in the proposed technique is detection and correction of the control-flow errors using both control-flow graph and data-flow graph. Using this technique, most of control-flow errors in the program are detected first, and...
Soft processors have become an increasingly common component of systems that use Field-Programmable Gate Arrays (FPGAs), and are used to implement a wide variety of control and data processing functionality. Often, some additional functionality needs to be added to a system when there is very little space left on the physical device. This functionality may not be performance critical, and so could...
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