The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This work demonstrates a new integrated inverse class E amplifier circuit, employing a pHEMT switching device and fully integrated output network for pulse shaping. The circuit is particularly suitable for full integration, since it does not need any RF choke for biasing, and no DC blocking capacitor is needed between the switch and the output network parallel resonance circuit. The back plate capacitances...
This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakage-reduction has been...
This paper presents the systematic design approach of a low-power, medium-resolution, high-speed pipelined Analog-to-Digital Converter (ADC). The ADC is implemented in 180nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB and effective number of bits of 9.64-bits at sampling speed of 50MHz with an input signal frequency...
The design plan and HSPICE measurement of a high acquisition speed for a sample of 8-bit CMOS differential successive approximation register (SAR) Analog-to-digital converter (ADC) are presented. The operation of the conventional main switch-capacitor array is divided into two switch-capacitor arrays. Such that, one switched-capacitor array is used to define the four most-significant bits, while the...
This paper presents and compares the performance of two controllers namely Fuzzy Logic and Proportional Integral applied to a voltage source inverter/converter operating as an active power filter. The active power filter is operated to compensate harmonics and reactive power generated by the non-linear load and power factor correction simultaneously. This work is performed in order to make an accurate...
This paper presents a low-power down-conversion mixer for 3.1~4.8 GHz MB-OFDM UWB applications. The proposed mixer is based on folded double-balanced Gilbert cell and employs following techniques: two cross-coupling capacitors at the transconductance stage enhance conversion gain and reduce input noise; two choke inductors reduce flicker noise from the switch quad; tuning capacitors and resistors...
Performance of the low-voltage and power-efficient analog-to-digital (A/D) converters, like cyclic and pipeline topologies, can be significantly enhanced by using advanced analog cores. This paper describes a careful switched capacitor (SC) architecture that can be used as a simple low-voltage implementation of the flip-around sample-and-hold (S/H) circuit. The S/H has been simulated in a 0.13 ??m...
This paper describes a new configuration of the single-phase seven-level voltage source inverter. The proposed inverter based on modified H-bridge converter. The inverter is built of conventional H-bridge inverter and two bidirectional switches and three bulk capacitor banks. To validate the proposed inverter, a low power prototype inverter has been designed and implemented; analytical, simulation...
The design and implementation details of a 4-bit time interleaved successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Low latency SAR ADC has been implemented by detecting two bits per clock cycle. Major contribution of this paper is that it uses only two capacitive DACs instead of three capacitive DACs. This is achieved by using...
A novel pixel readout circuit using a switched-capacitor integrator mode background suppression technique is proposed for long wavelength infrared (LWIR) focal plane arrays. It has ultra-low background suppression non-uniformity (BSNU) and no additional shot noise when suppressing the background current for improving signal-to-noise ratio and dynamic range. The BSNU can be as low as 529 ppm for a...
This paper proposes a new extended boost quasi Z-source inverter (ZSI) and a simple modulation and control method based on one-cycle control for controlling a grid connected PEM fuel cell energy system. ZSIs are gaining popularity. Similarly one-cycle controllers are becoming popular due to their simplicity, ease of implementation and fast response. However, this control method has not been developed...
Supercapacitors (SCs), as alternatives to conventional secondary batteries, need to be discharged as efficiently and deeply as possible to utilize precious stored energy. This paper proposes a novel SC discharger using cascaded switched capacitor converters (SCCs) and selectable intermediate taps. The proposed discharger roughly regulates the output voltage within a particular voltage range by selecting...
Voltage regulation in system-on-chip has turned into a very critical challenge for nanoscale IC designers. It is imperative that for multi-core implementation on-chip voltage regulator offers enormous benefits. This paper discusses the advantages and disadvantages of using on-chip regulators as well as their functional operation. Furthermore, it introduces the technique of using a hot swap controller...
A 10-bit successive approximation analog-to-digital converter (ADC), with offset correction circuitry and a tunable series attenuation capacitor is presented for implantable biosensor applications. The ADC is designed in a standard 0.13 ??m CMOS process technology and can operate with supply voltages down to 0.6 V. The ADC uses MOSFETs that are designed to operate in the sub-threshold region of operation...
In this paper, a modified auto zeroed integrator is used to design and simulate a low-voltage high-speed and accurate switched capacitor pseudo 2-path filter. The filter is a sixth-order Chebyshev band-pass filter operating at sampling frequency of 1MHz and center frequency of 250 kHz with a quality factor of 50. The circuit is simulated using HSPICE and 0.25??m CMOS technology.
A novel circuital model for a shunt connected RF MEMS coplanar switch, based on a fully analytical approach, is presented. The numerical simulations performed with the proposed new model are in good agreement with experimental measurements.
This paper presents the design and fabrication of fast DMTL RF MEMS phase shifters. Distributed MEMS Transmission Lines are being used with miniature RF MEMS switched capacitors (40times40 mum2), actuating at 25 V with a switching time around 1 mus. Both 90 and 180 degree phase shifters presented here operate at 20 GHz, are respectively less than 4.5 mm and 8.5 mm long. They are designed with 6 and...
Design an electrical locomotive 110 V D.C. source with PFC based on the structure of two-stage switching converter. Discuss the design scheme of main circuit and control circuit. Expound the calculation method of the key parameters. The experiments indicate that the device gets good performance on output and reliability. The electric source is appropriate for electrical locomotive and the other similar...
This paper presents a high-efficiency-high power density one stage ZVS-PWM single-ended push-pull (SEPP) high frequency inverter with new PFC functional scheme. This high-frequency resonant series load resonant inverter with lossless snubbing capacitors is composed of a passive PFC converter operating at one diode conducting bridge circuit and asymmetrical ZVS-PWM high frequency resonant direct inverter...
In this paper, a novel active boost converter for the SR drive is proposed. An active capacitor circuit is added in the front-end. Based on this active capacitor network, when the boost switch turns off, this network seems as a passive capacitor network. And the voltage of boost capacitor can keep balance with the DC-link voltage automatically. In the capacitor network, the discharging voltage is...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.