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The article describes the hardware architecture of computational units for the construction of GLONASS / GPS navigation user equipment. The described possible route to improve of some architectures based on field programmable gate arrays (FPGAs).
Multi-operand addition is found in many real-life applications. Field Programmed Gate Array (FPGA) has emerged as a platform for realizing digital systems. In this paper, we propose an approach for realizing multi-operand addition using ternary-adders on FPGAs. We focus on the case where the operands are of different sizes. The proposed approach reduces the area of the final implementation while reducing...
This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) for mixed-grained reconfigurable architecture (MGRA) with dedicated carry chains. The target MGRAs are assumed to have fine-grained blocks with dedicated carry chains to implement high-speed adders/subtracters and coarse-grained blocks to implement complicated arithmetic operations...
Implementing elliptic curve point multiplication (ECPM) based on residue number system (RNS) can efficiently use FPGA resources. In this paper, we propose a modular reduction method, where a kind of RNS pair is selected to achieve fast reduction. Our reduction method mainly needs several parallel additions while the reduction unit of previous designs require two multiplications which are computed...
Parallel FIR filter is widely used among various types of filter in Digital Signal Processing (DSP). This paper shows the design of area-efficient 2-parallel FIR filter using VHDL and its implementation on FPGA using image system. This paper gives the details basic blocks of area-efficient 2-parallel FIR digital filter. In this paper proposed 2-parallel digital FIR filter and area-efficient 2-parallel...
The Gabor filter has gained an important agreement in multimedia processing and visual search applications for its good spatial frequency and position selectivity, notwithstanding its heavy computational load. For these reasons, Gabor filters find useful applications in the processing of medical images, aiming to enhance the original image and to overcome issues related to noise and artifacts. With...
In the recent times we see that the digital signal processing applications are increasingly becoming complex which leads to the extensive using of the floating point numbers in the hardware processing implementations. In this paper, we will focus on the various advantages the HUB technique has when implemented on FPGA applications. The one advantage which the HUB floating point technique has that...
Compressors form the basic element of arithmetic circuits that are dominated by multi-operand addition operations. Compressor circuits based on carry-save logic have been used in past to realize parallel multipliers for ASIC implementation, however, owing to the peculiar architecture of FPGAs, these circuits do not map well on these platforms. In this paper, FPGA implementation of 4:2 compressor circuit...
Performance of adders has a tremendous impact on system-level functionality especially in signal processing applications. Carry Select Adder (CSLA) is one such adder which is proved to be a high speed version among other conventional adders. This paper presents a novel architecture for SQRT-CSLA with modified ripple carry adder chain. The pivotal feature of the proposed architecture is that the final-sum...
Field-programmable gate arrays (FPGAs) could outperform microprocessors on floating point computations due to massive parallelism, freedom on the selection of exponent/mantissa width, and utilization of simplified adders and multipliers. However, optimized use of resources and accuracy of the final implemented expression are two important issues in the implementation of floating point arithmetic expressions...
We propose the first hardware implementation of standard arithmetic operators - addition, multiplication, and division - that utilises constant compute resource but allows numerical precision to be adjusted arbitrarily at run-time. Traditionally, precision must be set at design-time so that addition and multiplication, which calculate the least significant digit (LSD) of their results first, and division,...
During the design of embedded systems, many design decisions have to be made to trade off between conflicting objectives such as cost, performance, and power. Approximate computing allows to optimize each objective, yet for the sake of accuracy. This means that a functional flaw is allowed to produce an error as long as this is small enough to maintain a feasible operation of the system or guarantee...
Image compression and size reduction increases the number of images stored on a memory space and reduces bandwidth consumption while increasing transmission speed on a communication channel. Images can be compressed and decompressed using different methods and algorithms. With the vast increase of quality and size, dedicated processors with parallel processing blocks such as FPGAs are mainly targeted...
DSP blocks are integrated in most modern high-performance FPGA devices in order to improve the speed and efficiency of computation-intensive DSP designs. Based on the existing ones, this paper proposes a new DSP block which can improve the speed and area-efficiency by reducing the delay of cascade path and supporting multi-input addition. Both architecture and implementation are described. Virtual...
This paper presents a 65nm ASIC based 256 NIST prime field ECC processor. To achieve high throughput, extensive pipelining techniques were applied to realize the Karatsuba-Ofman Multiplier along with enhanced NIST Reduction Formula. The processor architecture was implemented using Global Foundry 65nm Low Power (LPE) technology. The processor runs at a maximum frequency of 244 MHz and performs single...
Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a...
The experimental metastability characterizationof a flip flop requires a controllable delay with low jitter andhigh time resolution. In FPGAs such an experiment can bevery useful for in-situ or even online characterization of agiven flip flop, but existing solutions rely on the availability ofa digital clock manager (DCM) or a phase locked loop (PLL) for implementing this controllable delay. Given...
Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented...
Digital Signal Processors are special type of microprocessors with its architecture optimized for signal processing applications. Hardware acceleration has been proved as an extremely promising implementation strategy for the digital signal processing (DSP) and multimedia application domain. An accelerator module can be attached to processor core for enhancing performance. It enhances the performance...
This work presents the implementation of operant conditioning (OC) and classical conditioning (CC) with a single spiking neural network (SNN) architecture, thus suggesting that the two types of leaning may relate to the same cognitive process. Both are achieved by using a modified version of spike-timing-dependent plasticity (STDP), where the connection weight between a cue neuron and an action neuron...
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