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The main constraints in recent trends of VLSI technology are power, area and delay. CMOS designs occupy more area and dissipate more power. Power dissipation results in heating up of an IC which directly affects the reliability and performance. Multipliers are the integral part of major application systems like Microprocessor, Digital Signal Processor (DSP) etc., so it is necessary to optimize the...
This paper makes a comparison between various quasi-delay-insensitive (QDI) asynchronous ripple carry adders (RCAs) realized using a delay-insensitive dual-rail code which correspond to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The QDI RCAs considered are 32-bits in size and correspond to a variety of timing regimes viz. strong-indication, weak-indication, early output,...
One of the most crucial components in the computing devices is the full adders. The efficiency and effectiveness of arrays of full adders is essential; thus making it sensible to put in a reasonable effort towards improvisation of computational devices. In this paper, a new 1-BIT Full Adder (FA) with a combination of pass transistor logic and transmission gate logic is suggested. This new hybrid adder...
Full adder circuit is one of the most important digital functional block used in ALU. This paper presents a novel design of 8T full adder. The 8T full adder is designed on basis of a new logic 3T XOR and 2:1 multiplexer, in total of 8T. Compared to other existing full adders of 10T, 14T. There is significant improvement in power consumption, delay and power-delay product. For a supply voltage of 1V...
The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. A 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 90 nm technology. The results from...
In this paper, a review study and analysis of 1-bit full adder designs is presented with different logic styles such as Hybrid pass logic with static CMOS (HPSC), Hybrid and Hybrid-CMOS. Different styles of logic structures are used to design hybrid-CMOS namely pass transistor logic, complementary pass transistor logic (CPL), swing restoration CPL (SR-CPL) etc. So far the hybrid logic style provides...
In the era of advanced microelectronics, designing an energy efficient processor is a prime concern. Full adder is a most crucial unit in digital signal processing applications. This paper addresses the implementation of 1-bit full adder cell. In addition to this, AND and OR gate as an essential entity is also proposed with minimum hardware overhead. The circuit being studied is implemented using...
The widely using CMOS technology implementing with irreversible logic will hit a scaling limit beyond 2020 and the major limiting factor is increased power dissipation. The irreversible logic is replaced by reversible logic to decrease the power dissipation. The devices implemented with reversible logic gates will have demand for the upcoming future computing technologies as they consumes less power...
Reversible logic gates are implemented over a high scalein the future technologies. Reversible logic is seen as a demandingfield with variegated applications like CMOS designs consumingless power. This paper proposed design of a full Adder/Subtractorcircuitry with the help of fault tolerant based Reversible logic gates. In the given paper, a full adder/subtractor is proposed with help ofMIG (Modified...
Arithmetic circuits like adder, multiplexer etc. arethe most important circuits in digital signal processing andmany more applications. Full adder circuit is the basic cell ofarithmetic circuits. Many applications require circuits of highthroughput, small area and consume ultra-low power. In thisregards, this paper brings forward a new full adder circuitthat uses 10-Transistors and improved version...
This paper deals with the implementation of low voltage, energy efficient and high speed 1-bit Full Adder (FA) cell in pass transistor (PT) logic by using 20 nm compact model parameters. The existing full adder with pass transistor logic suffers from a drawback of replication of full swing in sum and carry outputs and voltage step existed in both the outputs at low to high transition. These will be...
The advancement in IC technology is primarily attributed to the MOSFET scaling theory. As the transistor size reduced, power consumption also reduced. As the process technology reached nano-meter regime, silicon CMOS started developing Short Channel Effects which led to increased power dissipation. A trade-off arose between power-dissipation and area. Alternatives to CMOS were found to avoid the trade-off...
Full adder cells play a vital role in numerous VLSI circuits. Therefore, design of an energy-efficient full adder which operates reliably in submicron technologies has become a great concern in recent years. Some previously designed cells suffer from non-full swing outputs, high-power consumption and low-speed issues. In this paper, two high-speed, low-power and full-swing full adder circuits are...
This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor...
Arithmetic logic unit (ALU) is an important part of microprocessor. In digital processor logical and arithmetic operation executes using ALU. In this paper we describes 8-bit ALU using low power 11-transistor full adder (FA) and Gate diffusion input (GDI) based multiplexer. By using FA and multiplexer, we have reduced power and delay of 8-bit ALU as compare to existing design. All design were simulated...
In this paper the design of multipliers which is less complex and power consuming is made of basic electronic components such as gates and adders. This design lowers the complexity of the circuit and works on the basic principle of multiplication and less number of transistors. The results show the multiplier is less complex and works effectively in large multiplications.
Designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Speed of the multiplier can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in a multiplication process one of them is array multiplier. array multiplier half adder have been used to sum the carry...
A full adder circuit is considered as one of the basic building blocks of Digital Signal Processors (DSPs), Arithmetic and Logic Units (ALUs), Application Specific Integrated Circuits (ASICs) and many other digital circuits and systems. Today, efficient full adder circuit design is one of the main challenges for VLSI engineers. This paper proposes a novel 1-bit full adder circuit designed using N-MOS...
This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 43% improvement in power-delay product (PDP). The proposed full adder provides full-swing output with good driving capability and it is a proper choice...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
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