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Full adder circuit is one of the most important digital functional block used in ALU. This paper presents a novel design of 8T full adder. The 8T full adder is designed on basis of a new logic 3T XOR and 2:1 multiplexer, in total of 8T. Compared to other existing full adders of 10T, 14T. There is significant improvement in power consumption, delay and power-delay product. For a supply voltage of 1V...
In this paper, a review study and analysis of 1-bit full adder designs is presented with different logic styles such as Hybrid pass logic with static CMOS (HPSC), Hybrid and Hybrid-CMOS. Different styles of logic structures are used to design hybrid-CMOS namely pass transistor logic, complementary pass transistor logic (CPL), swing restoration CPL (SR-CPL) etc. So far the hybrid logic style provides...
Full Adder is one of the fastest adder used in the complex data processing to perform fast arithmetic operations. The main aim of this paper is a design of 2T XOR gate based full adder using GDI technique.2T XOR gate is an absolutely necessary primitive in the design of full adder. Intension behind a novel method of 2T XOR gate based Full adder design is to reduce power improve the speed with an optimized...
In this paper, the design of a parallel self-timed adder by using transmission gate logic style was implemented for multi bit binary addition. Parallel Asynchronous Self Timed Adder (PASTA) is designed by using transmission gate based on recursive formulation. Multiplexer is used in this design for avoiding difficulties of interconnections. The operation is parallel to avoid carry chain propagation...
The integration of more and more number of transistors in a single chip leads to large amount of power dissipation. Scaling down of voltages to reduce power has its own limitation. As leakage current has a great contribution in the total power consumption of a circuit, we have come up with a methodology of power reduction by blocking the runtime leakage. This can be achieved by allowing no static...
With the shrinking technology, new systems are designed that are miniature in size and perform faster operations. Adder is a basic circuit used for the purpose of addition. In a cascade design, the output of one circuit acts as an input for the other, so delay in the propagation of the carry generated while addition is major issue in the design of adders. When the circuit is designed with any other...
To solve the serious problem of threshold loss that causes non-full-swing at the out-put of 1-bit full adder, an arrangement in which all the transistors are forced to operate in sub-threshold regime is proposed in this paper. But this will in turn bring additional area and delay overhead. In this work, full swing at the output of 1-bit full adder is retained with reduced area and delay overhead....
The key parameters for the performance measure of any VLSI design are logic delay, power consumption and chip area. This paper describes the VLSI design of a 16 Bit ALU and design is optimized in terms of Speed, Power Consumption and Chip Area. Different logic families are used in the design for various logic modules. The choice of logic families for each module is determined by considering speed...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
Multipliers play a key role in today's digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets — high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various...
We have designed the full Adder using hybrid-CMOS logic style by dividing it in three modules so that it can be optimized at various levels. First module is an XOR-XNOR circuit, which generates full swing XOR and XNOR outputs simultaneously and have a good driving capability. It also consumes minimum power and provides better delay performance. Second module is a sum circuit which is also a XOR circuit...
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