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This paper presents a floating point arithmetic modules which are useful for many real time applications such as FFT processor where complex butterfly operations are performed, in which precision and accuracy play a pivotal role in bio-medical and signal processing applications. When compared to fixed point representation, floating point arithmetic provides high precision which helps in increasing...
Vedic mathematics is a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras or formulae. This technique is very useful for performing tedious mathematical operations at a very fast rate. Motivated by this ancient mathematical system, a high speed low power 8-bit digital multiplier has been proposed in this paper based on Vedic multiplication algorithms...
Adders forms a major part in various arithmetic logical operations. Parallel Prefix Adder have been built up as the most essential and efficient circuit for binary addition. Their Particular structure and execution performance are very attractive for VLSI implementation. In these papers, we describe the design and performance of the Kogge Stone Parallel Prefix Adders and implemented using different...
Floating-point arithmetic plays major role in computer systems. Many of the digital signal processing applications use floating-point algorithms for execution of the floating-point computations and every operating system is answerable practically for floating-point special cases like underflow and overflow. The single precision floating point arithmetic operations are multiplication, division, addition...
Hardware acceleration has been proved as an extremely promising implementation strategy for the digital signal processing (DSP) and multimedia application domain. An accelerator module can be attached to digital signal processors for enhancing the performance. It enhances the performance or functionality by executing certain function in the accelerator instead of executing in the processor core. Adding...
Digital Signal Processors are special type of microprocessors with its architecture optimized for signal processing applications. Hardware acceleration has been proved as an extremely promising implementation strategy for the digital signal processing (DSP) and multimedia application domain. An accelerator module can be attached to processor core for enhancing performance. It enhances the performance...
Adders are one of most essential components of the digital circuits that are designed for different DSP applications. The important aspects considered for designing any digital circuit design are delay, power and Power Delay Product (PDP). In this paper, 32 bit carry bypass adders (CBA) which have superior performance with respect to these parameters are presented. The CBA's are implemented using...
Most important design parameter in integrated circuit is Power dissipation after speed. Adders are one of the basic fundamental component in such circuit, designing much efficient Adder results in optimizing whole circuit. Due to rapid growth in technology there is a need of fast processing arithmetic unit, so Carry Select Adder (CSLA) is one of the fast processing adder. By observing the CSLA circuitry...
A multiplier requires an Adder circuitry to add carry of previous result to next stage to form partial products and to get final result of multiplication. This paper presents a novel way to implement Line Multiplier without using Adders. The Adder-less Multiplier is implemented on both CMOS and FPGA platforms. In ASIC paradigm CMOS 90nm technology and on FPGA platforms Spartan-3 have been used for...
Power is one of the most important design parameter after speed, in integrated circuit. One of the basic fundamental component in such circuit is adder and subtractor. In order to optimize such circuits there is need of designing efficient and low power fundamental blocks. As per the Launder's principle, KTln2 heat is dissipated if there is any loss in bit. Excess-3 code is one of the sequential codes...
Approximate or inexact computing has recently attracted considerable attention due to its potential advantages with respect to high performance and low power consumption. This paper presents the design of an approximate multiplier; this approximate multiplier consists of an approximate Booth encoder, an approximate 4-2 compressor and an approximate tree structure. The approximate design is implemented...
With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device...
As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder on a VLSI based embedded application matters. In this paper we primarily deal with the construction of high speed adder circuits. Design...
Arithmetic unit design using reversible logic gate has received much attention as it reduces power dissipation with no loss of information. This paper proposes the design of 32-bit Binary Coded Decimal (BCD) addition and subtraction unit using reversible logic gates. The reversible 32 -bit BCD addition unit is designed using the following modules such as reversible 4-bit Carry Propagate unit using...
VLSI technology is an emerging field in the current technological scenario due to its advancements in fields of systems architecture, analog and digital logic and adders are the basic building blocks in digital integrated circuit based designs. The existing Ripple Carry Adder (RCA) has the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead Adder...
This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 43% improvement in power-delay product (PDP). The proposed full adder provides full-swing output with good driving capability and it is a proper choice...
This paper presents a new structure of 1-bit full adder for sub-threshold technology. It compares full adder sub-circuits and also compares the proposed full adder with common full adders in terms of propagation delay, power consumption, power delay product and square power delay product in sub-threshold technology. HSPICE simulations show that the power dissipation, power delay product and square...
Delay estimation is considered as one of the critical issues in the development of any Very Large Scale Integration (VLSI) design algorithms. It is also known as one of the factors to analyze in the design of high performance integrated circuit. Neither of these is usually applied to observe the performance of various VLSI topologies. High performance integrated circuits often use adders to achieve...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
A novel high speed booth encoder is designed by utilizing a new truth table. The important advantage of this structure is its low delay with respect to the previously presented papers. Moreover, generating partial products and putting the partial products array in order are done at the same time. Simulation results applied to the Hspice software in TSMC 0.18μm technology proves that the total delay...
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