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The increasing process variations which goes along with the continuing CMOS technology shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous Switching (MISS) is simplified to Single Input Switching (SIS) in most of the recent approaches, which introduces significant errors in Statistical Static Timing Analysis (SSTA). Hence, we propose a new modeling and statistical...
This paper introduces a bound-based approach to extract a pre-specified number of statistically-critical paths under process variations. These are the paths with the highest “violation probability,” which indicates the probability that a path would violate a given timing constraint. Our approach requires pre-computation of the violation probability of all the nodes and edges in the circuit timing...
Estimation of delay correlations is one of the most challenging problems in SSTA. This is because cell delay depends on a number of factors in a complex manner, which makes complex the estimation of correlations as well. In this paper, we introduce a technique to compute cell-to-cell and path-to-path delay correlations, which allows considering the effects of cell-level input/output edge, input slope...
With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic...
Statistical static timing analysis (SSTA) has been used in practice as an extension to regular static timing analysis (STA) to analyse for the impact of process variations on timing in new process nodes. However, the use of statistical timing in design optimization is a challenge that chip design teams face. In this paper, we propose some approaches to enable the comprehension of statistical timing...
As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Process variations in transistors affect circuit delay, resulting in serious yield loss. Considering the situations, variationaware designs for yield enhancement interest researchers. This paper investigates to exploit the statistical features in circuit delay and to cascade dependent instructions...
Statistical static timing analysis (SSTA) is indispensable for nanometer manufacturing under process variability. The process variations cause significant uncertainty in VLSI circuit timing and this makes yield control and timing verification a very difficult challenge. SSTA is suitable for timing estimation and design for manufacturability under process variation. However, most of the existing SSTA...
Asynchronous logic is a hot topic due to its interesting features of power saving, low noise and robustness to parameters variations. Beside of the benefits of asynchronous design technique, the lack of automatic design and analysis tools made it hard to apply them in the new designs. Timing analysis is a necessary step in automatic design process and optimization of asynchronous circuits. On the...
We introduce a bound-based technique to identify the top M timing-violating paths in a circuit under variability. These are the paths with the highest violation probability (i.e., Cp) which is the probability that a path (i.e., p) violates the timing constraint. To compute Cp, we require the violation probabilities of the nodes (i.e., Cn) and edges (i.e., Ce) on the path. First, we show computing...
In this paper, a grid-based multiple supply voltage (MSV) assignment method is presented to statistically minimize the total power consumption of 3-D IC. This method consists of a statistical electro-thermal simulator to get the mean and variance of on-chip, a thermal-aware statistical static timing analysis (SSTA) to take into account the thermal effect on circuit timing, the statistical power delay...
In this paper, we explore the implementation of Monte Carlo based statistical static timing analysis (SSTA) on a graphics processing unit (GPU). SSTA via Monte Carlo simulations is a computationally expensive, but important step required to achieve design timing closure. It provides an accurate estimate of delay variations and their impact on design yield. The large number of threads that can be computed...
While technology scaling has presented many new and exciting opportunities, new design challenges have arisen due to increased density, and delay and power variations. High-level synthesis has been touted as a solution to these problems, as it can significantly reduce the number of man hours required for a design by raising the level of abstraction. In this paper, we propose a new variation-aware...
This work addresses the new problem of timing variation-aware task scheduling and binding (TSB) for multiprocessor system-on-chip (MPSoC) architecture in the system-level design, where tasks have full flexibilities of resource (i.e. processor) sharing to meet the design constraints. With the timing variation of processors' clock speed, it has been observed that considering the effects of resource...
Due to the increased random variations in nanometer silicon process technology as well as voltage and temperature variations, it is very hard to guarantee performance characteristics with traditional corner-based timing analysis method. The variations, together with the issues like crosstalk and jitter, make it difficult to get a good silicon correlation with simulation and to meet target performance...
Due to the progress of nanometer process technologies, variability of circuit parameters is increasing and the statistical static timing analysis (S-STA) has been studied intensively. The existing block-based S-STA algorithms assume that the distribution of delay of each circuit element does not change through the analysis. However, such a delay depends on the input-slew, and the slew to be considered...
Statistical static timing analysis (SSTA) is becoming complicated due to introduction of more and more advanced statistical techniques. In this paper, with the help of conditional moments, we propose a simple path-based timing approach, which permits us to consider gate topology and switching process induced correlations. Numerical results are presented to quantify the relative impact of these two...
Statistical static timing analysis(SSTA) is an emerging technique that addresses increasing process variation effects on circuit behavior for designs at 65 nm and below. SSTA offers a number of advantages over traditional corner based static timing analysis(STA), most notably it provides a more realistic estimation of timing relative to actual silicon performance. Accurate statistical timing analysis...
This paper presents an adjustment-based modeling framework for statistical static timing analysis (SSTA) when the dimension of parameter variability is high. Instead of building a complex model between the circuit timing and parameter variability, we build a model which adjusts an approximate variation-aware timing into an accurate one. The intuition is that it is simpler to build a model which adjusts...
Satisfying timing constraint is the most important issue in today's VLSI design. The recent increase of process variation, however, made it too difficult to predict the circuit timing accurately using traditional deterministic methods. Many statistical static timing analysis (SSTA) approaches have been proposed to deal with the impact of large process variation effectively. However, most of them focused...
Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution functions (PDFs) rather than deterministically, have emerged to more accurately portray integrated circuit performance. This analysis has been thoroughly performed on traditional zero clock skew circuits where the synchronizing clock signal is assumed to arrive in phase with...
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