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This paper presents a methodology for reducing functional test time in subthreshold SoCs targeting ultra-low power (ULP) internet-of-things (IoT) devices. Due to their low operating speed and voltage, subthreshold SoCs require significantly longer time to test than traditional SoCs. The proposed method models trans-threshold correlations to allow high voltage, high speed testing while accurately predicting...
The problem of determining the sensitization probability of a path by a test vector is investigated. It is important when testing for delay defects due to process variations. An algorithm is presented which has high accuracy. Gate delays are modeled as probability mass functions, and novel operations are introduced that take into consideration circuit reconvergences and path correlations. Experimental...
Consider a set of random sequences, each consisting of independent and identically distributed random variables drawn from one of the two known distributions $F_{0}$ and $F_{1}$ . The underlying distributions of different sequences are correlated, induced by an inherent physical coupling in the mechanisms generating these sequences. The objective is to design the quickest data-adaptive and sequential...
In the nanometer era where the operating speed of a chip decides its price, design companies rely on high-qualty speed binning approaches to maxmizie their profits. The conventional speed binning approach is legacy (i.e. structural) since functional tests are too expensive to derive. Besides legacy and functional tests, recent studies tried to apply the notion of delay testing for deriving speed-binning...
Differences in power supply noise (PSN) between functional and structural delay testing can lead to differences in chip operating frequencies of 30% or more. High delay correlation between structural and functional test requires the paths under test to experience the worst-case realistic PSN. We present a PSN control method for pseudo functional test that combines random flipping and background patterns...
Cloud computing security is one of the main concerns preventing the adoption of the cloud by many organisations. This paper introduces mitigation strategies to defend the cloud specific CIDoS class of attacks (Cloud-Internal Denial of Service), presented in [1]. The mitigation approaches are based on techniques used in signals processing field. The main strategy to detect the attack is the calculation...
Power Supply Noise (PSN) has emerged as an important resilience issue in nano-scale CMOS technology. Due to simultaneous switching of various gates, the actual supply voltage seen by individual gates inside the circuit might be lower than the nominal supply voltage, leading to extra delays. Since in at-speed scan testing simultaneous switchings are higher than the functional mode, test invalidation...
When testing multithreaded programs, the number of possible thread interactions makes exploring all interactions infeasible in practice. In response, researchers have developed concurrent coverage metrics for multithreaded programs. These metrics allow them to estimate how well they have exercised concurrent program behavior, just as branch and statement coverage metrics do for sequential program...
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