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This paper presents a novel switching scheme for an ultra-low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme employs unit capacitors for voltage sampling and charge redistribution. Compared with previously published capacitive DAC which uses the same unit size of capacitor array,...
A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed...
A biomedical electronics interface to detect heart signals is presented including a reconflgurable full differential fifth-order Bessel Gm-C filter and a 12 bit low-power fully differential successive approximation register analog-to-digital converter (SAR ADC). The total fully differential structure reduces the input signal noise and distortion effectively. A switch array is used in Gm-C filter to...
Analysis and experimental results for a new switching scheme and topology for charge sharing DACs used in successive approximation register (SAR) ADCs is presented. The characteristics of the SAR algorithm are exploited to develop a switching scheme that reduces the number of required unit capacitors by nearly an order of magnitude over conventional charge sharing DACs without the aid of any additional...
A voltage feedback charge-cancellation technique is proposed which prevents the conversion nonlinearity due to the parasitic effect of split DAC architecture in Successive Approximation Register (SAR) ADCs. A voltage feedback network operating as a capacitive charge-pump can efficiently detect and compensate the voltage error in each bit cycling, thus the conversion accuracy can be significantly improved...
This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.
A voltage feedback charge compensation technique is presented to prevent the conversion nonlinearity due to the parasitic effect of split capacitive DAC structure in successive approximation register (SAR) ADCs. The charge compensation is achieved by using an open loop amplifier that performs voltage feedback to the DAC array via a compensation capacitor, which is easy to be implemented with very...
An ultra low-energy successive approximation (SA) Analog-to-Digital Converter (ADC) is presented. The proposed ADC uses an energy-efficient unit capacitor array having a new switching arrangement in DAC for passive charge re-distribution. Reference levels are generated sequentially to get successive bits. The proposed method is analyzed theoretically and compared with other methods. Mathematical analysis...
A successive approximation ADC based on the C2C DAC architecture is introduced. The ADC designed in a 0.18 ??m CMOS 2 Poly 4 Metal process uses a hybrid capacitive DAC combining the best of the binary weighted capacitive array and the C2C array. C2C ladder based architectures are very attractive for implementation because of its small area, high speed and low power consumption. However a major drawback...
This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling step with dual sampling of the analog signal. By sampling and holding the analog signal asymmetrically at both input sides of comparator, the MSB cycling step can be hidden by hold mode. Benefits from this technique, not only the total capacitance of DAC is reduced by half, but also the average switching energy is reduced...
Capacitance matching is a critical issue in several analog and mixed-signal designs such as switched-capacitor filters, A/D and D/A converters. Using identical unit capacitors in parallel to implement each capacitor in the design, combined with a careful layout, is the best technique to achieve a good capacitance matching. Common-centroid geometry is the most widely used layout technique for matching...
This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At...
A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18 mum standard CMOS technology. This ADC has signal...
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