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In this paper we propose a variable-gain transimpedance amplifier suitable for low-power applications. Its noise, bandwidth and input impedance performance are similar to a more conventional regulated-cascode common-gate transimpedance with resistive load, with the same power consumption and gain performance. The proposed amplifier has, however, variable gain, which can be easily changed by setting...
This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated for the...
This paper proposes the design and analysis of a broadband 2-40 GHz passive distributed drain-pumped mixer using 0.18 μm CMOS technology for ultrawide-band (UWB) receivers. To achieve broad bandwidth for the UWB communications, a distributed topology is introduced. A closed-form analytical model for the conversion loss of distributed drain-pumped mixer is presented for the first time. The designed...
A 1.1 mW 87 dB dynamic range 3rd order ΔΣ modulator is implemented in 0.18 μm CMOS technology for the audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed and only one simple current mirror single-stage OTA with 34 dB DC gain is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB...
An optimum gate-loaded cascode topology for maximizing the gain of a stable CMOS amplifier in micro/millimeter wave band is presented. By adding a piece of transmission line in the gate of cascode transistor, choosing an appropriate matching circuit that includes biasing, and exploiting the proper transmission line structure the gain per stage of CMOS amplifier can be increased and an optimum design...
A low-power ultra-compact CMOS low-noise amplifier (LNA) in a shunt-resonating current-reused topology is presented. The common-source transistors are connected with a shunt-resonating inter-stage match network such that the bias current is shared to have low power consumption and RF signal is doubly amplified to have high gain and low noise figure. The implemented 0.18 mum CMOS LNA achieves 15.2...
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