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Network-on-Chip (NoC) has emerged as a solution for communication framework for high-performance nanoscale architecture. One important aspect, in addition to deadlock-free routing, is low power consumption. In view of varied communication requirements, application specific SoC design is increasingly important. Customized NoC architectures are more suitable for a particular application, and do not...
Networks on chip (NoC), a new packet-based design method, with a new dependable no deadlock (DND) back-tracking routing algorithm are proposed to implement artificial neural network (ANN). This system is simulated by NIRGAM NoC simulator to get system performance. Experimental results show that this proposed system has higher connection-per-second (CPS), lower communication load than the exiting other...
Networks-on-Chip (NoCs) are becoming widespread in contemporary multi-core and many-core designs. Amongst their appeals are regularity of layout and flexibility of topology. However, the energy consumed by routing nodes is now vastly more than that of an ALU operation in one of the processing cores they service. We present an evaluation of bypassing, a technique where selected traffic can avoid the...
This paper describes theoretical as well as practical aspects in designing low phase noise LC CMOS oscillators. It starts with an overview of the different oscillator performance parameters found in a typical oscillator specification sheet. It also describes the LC-tank oscillation phenomena by analyzing a simplified LC oscillator circuit. Oscillator phase noise analysis is then introduced as a logical...
In this contribution a new balanced biphase modulator topology is presented. The new biphase modulator allows the reduction of the resulting chip area occupation by using 3 couplers only, in contrast with traditional reflection-type balanced biphase modulators with 4 couplers, and exhibiting comparable performances. A 45-65 GHz test vehicle adopting the proposed topology has been designed and realised...
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