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Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD includes TSV models, improves models for 2D off-chip...
A wide-band lumped element model for a through silicon via (TSV) is proposed based on electromagnetic simulations. Closed form expressions for the TSV parasitics based on the dimensional analysis method are introduced. The proposed model enables direct extraction of the TSV resistance, self-inductance, oxide capacitance, and parasitic elements due to the finite substrate resistivity. The model's compactness...
Simulator accuracy is an important, but seldom examined, part of study on 3D integration. This paper examines inaccurate technology parameters as a source of error for the CACTI and PRACTICS cache simulation tools. By replacing the default parameters with ones derived from information made available in the literature, CACTI simulation error for the 90 nm Itanium2 L3 cache is eliminated almost entirely...
In this paper, we present a layout driven approach used to fill empty space within MCM, with 3D high density decoupling capacitors. In a first time, a description of the innovative 3D unit cell is done based on process considerations. Then the method including the whole design flow is described and validated with the help of specific test cases and RF characterization data up to 6 GHz. A physical...
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