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Convolutional Neural Networks are being studied to provide features such as real time image recognition. One of the key operations to support HW implementations of this type of network is the multiplication. Despite the high number of operations required by Convolutional Neural Networks, they became feasible in the past years due the high availability of computing power, present on devices such as...
This paper proposes a low complex hardware accelerator algorithmic modification for n-dimensional (nD) FastICA methodology based on Coordinate Rotation Digital Computer (CORDIC) to attain high computation speed. The most complex and time consuming update stage and convergence check required for computation of the nth weight vector are eliminated in the proposed methodology. Using the Gram-Schmidt...
We present a set of tools for digital design, integration and verification of mixed-signal Application Specific Integrated Circuits (ASIC) developed within our design team. We have chosen Python for the development of the tools. By drawing on Python's features we have developed tools targeting many steps required across a design flow: a) Complex digital blocks are auto-generated, where Python generates,...
Underwater communication with autonomous underwater vehicles (AUVs) has strong demands on the modems caused by the constantly changing signal propagation (multi-path propagation, scattering, diffraction and refraction at thermal layers, etc.) of the underwater channel. These demands typically lead to a modem designed to match specific conditions. In this paper we present an automated model-based physical...
High level synthesis tools offered by either FPGA (Field Programmable Gate Array) vendors or from the public domain are evaluated in order to generate efficient and low complexity computational intelligence modules. This paper reports specific issues and comparative synthesis results in implementing basic modules of the FSVC classifier (Fast Support Vector Classifier) and cellular automata starting...
Traditional processor design approaches using CISC and RISC philosophies suffer from low performance. One of alternative approaches to improve system performance is instruction level parallelism (ILP). Among the processor architectures supporting ILP, very long instruction word (VLIW) processors offer some advantages such as low power consumption and hardware complexity. In this paper, we introduce...
In the field of underwater acoustic communication, because of the signal transmission distance is shorter, generally uses the copper cable transmission. When the signal is needed to be transmitted in a long distance, its anti interference and attenuation will seriously affect the reliability of the transmission. Optical fiber transmits in higher speed and stronger antijamming. Its application is more...
Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC). Therefore, in this paper, two pixel correlation based computation and energy reduction techniques for HEVC fractional interpolation are proposed. The proposed pixel equality based computation reduction (PECR) technique does not affect the PSNR and bit-rate. The proposed pixel similarity...
Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
We introduce PyRTL, a Python embedded hardware design language that helps concisely and precisely describe digital hardware structures. Rather than attempt to infer a good design via HLS, PyRTL provides a wrapper over a well-defined "core" set of primitives in a way that empowers digital hardware design teaching and research. The proposed system takes advantage of the programming language...
In recent years, synthetic test instruments have become increasingly popular in the automatic test equipment (ATE) market. This type of instrument gives users the ability to create custom solutions to better meet their test requirements. FPGA (Field Programmable Gate Array) based solutions are the most common synthetic test instrument on the market today. FPGA based solutions can work well due to...
Today's dominant hardware description languages (HDLs), namely Verilog and VHDL, tightly couple design functionality with timing requirements and target device constraints. As hardware designs and device architectures became increasingly more complex, these dominant HDLs yield verbose and unportable code. To raise the level of abstraction, several high-level synthesis (HLS) tools were introduced,...
This paper proposes a hardware accelerator for n-dimensional (nD) FastICA methodology, introducing the concept of Vector Cross Product into the Coordinate Rotation Digital Computer (CORDIC) based FastICA to attain high computation speed. The complete FastICA Iteration stage required for computation of the nth weight vector is eliminated by using Vector Cross Product in nD FastICA. Introducing Vector...
In this contribution, we present a coverage driven functional verification environment based on the UVM framework and the System Verilog language to certify the operational correctness of the ECC error management logic used in volatile and nonvolatile memories. We apply this methodology to floatinggate nonvolatile memories for the embedded market, which requires a read error rate of 10−14. The proposed...
Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level synthesis can be employed instead, in order to automatically obtain HDL codes from highlevel language functional descriptions. With high-level synthesis it becomes easier to design coprocessors, accelerators, and other special-purpose hardware. Nonetheless,...
Open source hardware projects are becoming more and more common. OpenRISC SOC, one of the prominent of these projects, has become quite popular with the support of volunteer developers. In this work, we have demonstrated the design of an DES (Data Encryption Standard) based system, that can be used in security applications, on ORPSoC-v2 (Openrisc Reference Platform System-on-Chip). Additionally, we...
FPGAs have emerged as a cost-effective accelerator alternative in clouds and clusters. Programmability remains a challenge, however, with OpenCL being generally recognized as a likely part of the solution. In this work we seek to advance the use of OpenCL for HPC on FPGAs in two ways. The first is by examining a core HPC application, Molecular Dynamics. The second is by examining a fundamental design...
A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
Due to the proliferation of reprogrammable hardware, core designs built from modules drawn from a variety of sources execute with direct access to critical system resources. Expressing guarantees that such modules satisfy, in particular the dynamic conditions under which they release information about their unbounded streams of inputs, and automatically proving that they satisfy such guarantees, is...
Non-linear solar photovoltaic (SPV) system characteristics and its dependency on meteorological variables of irradiance and temperature; renders this energy source rather involved to visualize. In this paper a low power realtime SPV module simulator is realized in field programmable gate array (FPGA) XCS100E platform for classroom teaching. FPGA platform is used due to its parallel computing nature...
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