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This paper presents the design of a Coarse-grained Reconfigurable Architecture (CGRA), called MUSRA (Multimedia Specific Reconfigurable Architecture). The MUSRA is proposed to exploit multi-level parallelism of the computation-intensive loops in multimedia processing applications. To solve the huge bandwidth requirement of parallel processing arrays, the proposed architecture focuses on the exploitation...
Support Vector Machines (SVM) are considered as one of the most commonly used pattern recognition techniques for various applications. In this paper, a novel attempt is made to design and implement SVM classifier using Reconfigurable architecture on a Xilinx Virtex-5 FPGA. The performance of proposed reconfigurable system is compared with its conventional non-reconfigurable architecture and the results...
Due to their flexibility and high performance, Coarse Grained Reconfigurable Array (CGRA) are a topic of increasing research interest. However, CGRAs also have the potential to achieve very high energy efficiency in comparison to other reconfigurable architectures when hardware optimizations are applied. Some of these optimizations are common for more traditional processors but can also lead to large...
As the power wall has become one of the main limiting factors for the performance of general purpose processors, the trend in High Performance Computing (HPC) is moving towards application-specific accelerators in order to meet the stringent performance requirements for exascale computing while still satisfying power budget constraints. Within this context, reconfigurable devices, and more specifically...
Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level reconfigurable abstractions. Both fine-grain and coarse-grain architectures (e.g. CGRAs) traditionally require low level programming and suffer from long...
Embedded System Reconfigurability has begun since few years thanks to the FPGA capabilities. Many approaches and methodologies have been adopted in literature. Several tools were proposed to designers, but a big luck of efficiency has been noticed. So several works studied this concept and still looking for the best tools and flow. This paper presents an overview of Reconfigurability concepts and...
NoC based SoC FPGAs are a promising technology for high performance embedded systems because they provide a good balance between performance, rapid time to market, cost and flexibility. The reconfigurability aspect of FPGAs allows FPGA platforms to adapt themselves to the various processing requirement of applications. On the other hand, many applications are designed in such a way that their quality...
The DARPA Arrays at Commercial Timescales (ACT) program seeks to lower the nonrecurring engineering costs and timeframe of designing and upgrading phased arrays through the use of a common hardware module that can be reused across many phased array missions and array sizes. The ACT program seeks to utilize elemental level digital beamforming to remove many of the fixed choices, e.g. array size, number...
This paper presents a framework for hardware and software co-design to building systems designed to driver assistant using computer vision. This work is part of a doctoral research project nearing completion. To validate the model, a modular pedestrian detection is implemented by comparing the results obtained with other design.
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based systems that allows to achieve high quality results in terms of overall application execution time. The proposed algorithm exploits the notion of resource efficient task implementations in order to reduce the overhead incurred by partial dynamic reconfiguration and increase the number of concurrent tasks...
As location sensing devices are becoming ubiquitous, overwhelming amounts of data are being produced by the Internet-of-Things-That-Move. Though analyzing this data presents significant business opportunities, new techniques are needed to attain adequate levels of processing performance. One example is the recently introduced geohash geographical coordinate system that is mainly used for indexing...
In this paper, we propose a reconfigurable architecture for discrete cosine transform (DCT) computation. The objective of the paper is to integrate the DCT computation in a complete embedded system based on ARM processors. Based on dynamic partial reconfigurable FPGAs, different versions of DCT computation are used to give adaptability and flexibility to the architecture. These adaptability responses...
Analyzing the volume, variety and velocity of big data requires the use of modern heterogeneous computing platforms composed of multicores with SIMD execution units, GPUs, clusters, FPGAs and in the future new reconfigurable architectures. However, programming in this environment is extremely challenging due to the need to use multiple low-level programming models and then combine them together in...
Hardware reconfigure model provides flexibility to same hardware for different application. Coarse-grained Architecture (CGRA) is best example of the reconfigurable system. This paper proposed and configuration memory based CGRA system which can change the hardware Configuration dynamically according to applications. Configuration memory will consist of multiple such DFGs that will configure the hardware...
This article consists of a collection of slides from the authors' conference presentation. Are FPGAs a Promising Target in the Datacenter for Deep Learning? Yes.
Recent work in the field of analog computing has shown that electronic emulation circuits are of large interest when targeting the speed of routines dedicated to power systems. In this paper, a power flow implementation is presented that is tailored to such a mixed-signal computing platform. A computation time of a few microseconds per algorithm iteration is reported. This time is also almost independent...
A new class of low-cost satellites has the potential to reduce the cost of traditional space-based services. Unfortunately, to date, low-cost satellites have proven to suffer from poor reliability. While traditional techniques for increasing reliability are well known to satellite developers, these techniques are poorly suited for implementation on low-cost satellites due to intrinsic budgetary, mass...
This paper presents a fault-tolerant hardware architecture for robust wearable heart rate monitoring. The proposed architecture is designed for fusion of the heart rates estimated from both electrocardiogram (ECG) and arterial blood pressure (ABP) signals, with small hardware footprint and low energy consumption. It benefits from the following unique features: (1) an optimized heart beat (peak) detection...
Nowadays, there can be identified at ease a number of significant areas based on a conventional digital circuitry, such as evolvable or adaptive hardware, fault-tolerant architectures, reconfigurable systems or circuit development, where the introduction of partial reconfiguration principles may bring significant benefits with respect to traditional approaches. In case of polymorphic digital circuits...
Automation Systems have to deal with breakdowns of their components which potentially lead to drop-off in production and high follow-up costs. The current solution for this problem is the use of redundant hardware ensuring high availability but causing high costs. Starting from nowadays often used distributed automation systems, this paper proposes a software-based solution for high availability using...
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