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As feature sizes decrease, soft errors are expected to become the dominant failure mechanisms for integrated circuits. This paper discusses the challenges that design and reliability engineers will face with the manufacture and test of ICs at advanced technology nodes.
Pre-bond testing of 3D ICs improves yield by preventing bad dies and/or wafers from being used in the final 3D stack. However, pre-bond testing is challenging because it requires special scan chains and power delivery mechanism. Any 3D scan chains that traverse multiple dies will be fragmentized in each individual die during pre-bond testing. In this paper we study the scan chain and power delivery...
At-speed delay testing is inevitable for improving the test quality of modern high-speed semiconductor chips. This paper presents a scan cell architecture for at-speed testing of delay faults in inter-clock logic. The technique utilizes commercially available ATPG tools for test pattern generation and internal PLL clocks for test pattern application. The hardware modification is contained within the...
Customer returns are defective parts that pass all functional and parametric tests, but fail in the field. To prevent customer returns, this paper analyzes wafer probe test data and tries to understand what it takes to screen them out during testing. Because these parts pass all tests, analyzing their signatures based on the original test perspective does not make sense. In this work, we search for...
System-level interconnect structures become much more complicated and dominate overall performance in multi-core systems. In order to facilitate interconnect test in board-level and system-on-chip (SoC) designs, IEEE standards 1149.1 and 1500 are developed. Dedicated design-for-testability (DFT) architectures for interconnect consisting of through-silicon via (TSV) in future 3-D stacked ICs have also...
Timing analysis is a key sign-off step in the design of today's chips, but as technology advances, it becomes ever more challenging to create timing models that accurately reflect real timing-related behavior. Complex dependencies on second order phenomena, such as pattern density and stress/strain make it very difficult to develop device models and simulation tools that accurately predict the timing...
Three-dimensional Stacked IC (3D-SIC) is a promising technology gaining a lot of attention by industry. Such technology promises lower latency, lower power consumption and a smaller footprint as compared to planar ICs. Reducing the overall 3D-SIC manufacturing cost is a major challenge driving the industry. The process of stacking the dies together is an integral part of 3D-SIC manufacturing process;...
Wafer testing via direct-contact probe cards has long been an effective and relatively low-cost method for testing integrated circuit (IC) chips prior to packaging. However, the physical contact occurring between the wafer and automatic test equipment (ATE) has significant costs due to contact point deformation and the need for abrasive cleaning. In this paper, we investigate a non-contact testing...
The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 μm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.
In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan...
No Trouble Found (NTF) and Cannot Duplicate (CND) errors on modern digital electronics are increasingly prevalent and occur at a rate of 50-60% using conventional bench top diagnostics. This work correlates NTF diagnostic errors to Negative Bias Temperature Instability (NBTI), a prominent failure degradation mode and self annealing mechanism in sub-100 nm CMOS technology. NBTI degradation is duplicated...
This paper presents the results and methodology of recent system-level proton testing which was performed on a COTS-based GPS receiver to be used in a launch vehicle application. Susceptibility to ionizing radiation was a concern due to a high part count and component sophistication. Testing was conducted using 50 MeV protons at the Lawrence Berkeley National Laboratory (LBNL). An approach for the...
Negative Bias Temperature Instability (NBTI) has emerged as the dominant PMOS device failure mechanism in the nanometer VLSI era. The extent of NBTI degradation of a PMOS device increases dramatically at elevated operating temperature and supply voltage. Unfortunately, both these conditions are concurrently experienced by a VLSI chip during the process of burn-in testing. Our analysis shows that even...
Electrical bugs, such as those caused by crosstalk or power droop, are a growing concern due to shrinking noise margins and increasing variability. This paper introduces COBE, an electrical bug modeling technique which can be used to evaluate the effectiveness of validation tests and DfD (design-for-debug) structures for detecting these errors in post-silicon validation. COBE first uses gate-level...
We present an application of Defect Oriented Testing (DOT1) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge...
3D integration of ICs is an emerging technology where multiple silicon dies are stacked vertically. The manufacturing itself is based on wafer-to-wafer bonding, die-to-wafer bonding or die-to-die bonding. Wafer-to-wafer bonding has the lowest yield as a good die may be stacked against a bad die, resulting in a wasted good die. Thus the latter two options are preferred to keep yield high and manufacturing...
Delay testing is performed to guarantee that a manufactured chip is free of delay defects and meets its performance specification. However, only few delay faults are robustly testable. For robustly untestable faults, non-robust tests which are of lesser quality are typically generated. Due to significantly relaxed conditions, there is a large quality gap between non-robust and robust tests. This paper...
This paper describes latest RF ATE (Automated Test Equipments) technologies including DUT (Device under Test) connections, calibration method as well as RF test module. A major interest of RF test is cost of test (COT). Most important respect for low COT is how achieve a number of simultaneous measurements and short test time. We realized the both respects by drastically downsized RF test module with...
3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing...
This paper attempts to present a novel low-cost testing method for the measurement of band-pass filter testing. The study directs our attention to reduce the cost of test using a simple circuit such as a down-convertor mixer. The band-pass filter is tested by inputting the five critical frequency points. And then the five data which the high frequency had been converted down to 20MHz were collected...
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