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Routing algorithms can improve network performance by maximizing routing adaptiveness but can be problematic in the presence of endpoint congestion. Tree-saturation is a well-known behavior caused by endpoint congestion. Adaptive routing can, however, spread the congestion and result in thick branches of the congestion tree — creating Head-of-Line (HoL) blocking and degrading performance. In this...
The design space exploration of Networks-on-Chip (NoC) requires tools to evaluate the network performance, tune its parameters and achieve the requirements of the target application. In this context, this paper presents RedScarf, a simulation environment with graphical user interface and a set of tools that automate the design space exploration of NoCs. It presents many resources that make RedScarf...
Simulation is one of the main tools used to analyze new proposals in the Network-on-Chip (NoC) field. Among these simulators for analyzing and testing new ideas in NoC architectures, the Noxim simulator stands out, being used by many researchers due to the wireless support and open-source availability. An important issue at the simulation phase is the choice of workload, as it may affect testing the...
Network-on-Chip provides scalable communication in Systems-on-Chip with many Intellectual Property cores. Studies have shown that unutilized router buffers lead to significant network performance degradation. This work presents Roundabout, a new asynchronous router architecture with inherent and effective buffer utilization. Inspired by real-life multi-lane roundabouts, it consists of lanes shared...
With the widely using of network-on-chip in VLSI systems, mapping has been one of the most critical and general problem in VLSI design and test. In this paper, a breadth-first greedy algorithm is proposed to reduce internal congestion and solve the application mapping with the structure of the task topology and the shape of the mapping area. The experimental results show our solution achieves the...
Emerging neural network accelerators are often implemented as many-core chips and rely on a network-on-chip to handle the huge amount of inter-neuron traffic. The wellknown mesh and tree are the most popular topologies in prior many-core neural network accelerator designs. However, these conventional topologies suffer from high diameter, low bisection bandwidth, and poor collective communication support...
Most correspondence movement in today's Network on Chips (NOC) depends on switch for unstable memory based outlines. The NOC ought to be intended to effectively deal with the many-to-one correspondence design, information access to and from the directing controller. This paper rouse the utilization of partitioned system for steering and legitimize the power utilization and execution change is gotten...
The NoC Architecture plays crucial role while designing communication systems for System on Chip (SoC). The NoC architecture is improved over conventional bus, shared bus design and cross bar interconnection architecture for on chip networks. In order to improve the Quality of Service, Congestion, Throughput and latency in NoC, Hexagonal node based architecture is proposed in our previous paper[14]...
Built-In-Self Test (BIST) being one of the techniques which are well known for their ability of providing on-chip testability feature, attracts its usage in today's System-on-Chip (SoC) designs. With the evolution of Network-on-Chip (NoC) communication for complex SoC, the need for fault tolerant systems have increased at a speed. In an attempt to design a good BIST architecture, this paper proposes...
With 3D NoCs help improve circuit performance, fault tolerance and energy efficiency through the reduction of average wire-length and the increase in communication bandwidth of on-chip wiring, the soaring increase of on-chip temperature remains one of the most challenging obstacles to their commercialization. We present a physical design flow that integrates thermal driven floor-planning with MOEA...
Table-based routing is a common approach for a fault-tolerant Network-on-Chip (NoC). This approach is hard to scale, since the table size tends to grow according to the NoC size. To surpass this problem, some works, such as the Region-Based Routing (RBR), have proposed techniques for saving routing tables area. This work proposes an alternative routing technique finding among communication pairs selected...
As an interconnection topology, two-dimensional mesh is widely used in the design of the network-on-chip (NoC) for integrating dozens of cores on a VLSI chip because of its very simple structure and ease of on-chip implementation. However, as the progress of IC technology, it becomes possible to integrate a large-scale system on a chip that contains more than one thousand processing elements or cores...
The emergence of Network-on-Chip (NoC) as a communication paradigm for Multi-Processor System-on-Chips (MPSoCs) significantly exacerbates the need to provide a methodology that optimizes the energy consumption of the overall system. This is especially important when factoring in current Network-on-Chip advances which have multiple communication media such as on-chip wireless or nano-photonics links,...
Network-on-chip (NoC) emerged as a promising alternative to the bus and point-to-point communication architectures. Recently 3D NoC become a hot topic. While complex 3D NoCs will generate a large amount of data to deal with, NoCs suffer from intermittent congestions and link overflows, especially when the network bandwidth is limited by the area and energy budget. In this paper, we explore a technique...
As the current decade is witnessing a shift from traditional System — On — Chip (SoC) to Network — On — Chip, but the inherent problems such as congestion, latency and delay still remains the major issues of concern. The effect of these issues in a chip may somehow be minimized by carefully designing a topology and a suitable routing algorithm which offers both path diversity and scalability. In this...
Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for...
The susceptibility of on-chip communication links and on-chip routers to faults has guided the research towards focusing on fault-tolerance aspects of 2D and 3D Network-on- Chips (NoCs). In this paper, we propose Logic-Based Distributed Routing for 3D NoCs (LBDR3D), a scalable, re-configurable and fault-tolerant mechanism, which utilizes only two virtual channels for implementing any deadlock-free...
Due to increasing number of cores, the placement of the cores onto NoC platform has become an important issue. If we can map the application cores close to each other to place them with more communication requirements, the performance parameters will improve and the network will be more efficient. In this paper, we propose a low complexity heuristic algorithm for the application mapping onto NoC to...
As we know, mapping is one of the most important steps in the process of network on chip. If we can map the application cores close to each other to place them with more communication requirements, the performance parameters will improve and the network will be more efficient. In this paper, we propose a low complexity heuristic algorithm for the application mapping onto NoC to improve latency. In...
One of the greatest challenges with cutting edge technology in System-on-Chip (SoC) is capability of processing core especially for complex and larger network size interconnections. Additionally, it is important to consider the effectiveness of routing algorithm in the overall performance of Network-on-Chip (NoC). Hence, the design and implementation of networks-on-chip should be considering aspects...
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