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This paper investigates the use of stacked depletion-mode n-channel MOSFET (D-MOS) for RF switch applications. Compared to the commonly used enhancement-mode MOSFET (E-MOS), the D-MOS transistor offers a significant reduction in on-state resistance (RON) and off-state capacitance (COFF) simultaneously and an excellent figure of merit (RonX Coff) of 134fs (roughly 3X improvement) can be achieved. With...
Intel® introduced an energy efficient SoC power delivery scheme utilizing fully-integrated high-frequency voltage regulators along the roadmap of Moore's law scaling. From 22nm process to 14nm or even 10nm, circuit blocks shrink and the embedded passives are scaled sequentially in the similar manner. A major challenge in the on-die VR design is to achieve sufficient integration and minimization of...
The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus minimising any hot carrier injection and dielectric stress degradation. The presented voltage extension technique is scalable to larger and smaller...
The design and operation of an asynchronous two-input mutual exclusion element are described in this paper. A decision-making module suitable for implementing n-way decision-making circuits is also implemented using CMOS DVCS logic.
A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13µm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing...
Complex metal oxide (CMO) e.g. Pr1−xCaxMnO3 (PCMO) based resistance random access memories (RRAM) are non-filamentary which leads to forming-less operation, low variability and area scalability of current [1]. However, both CMO and TMO based RRAM show poor nonlinearity. Hence, various nonlinear selector devices (e.g. oxide based selectors [2]) have been explored. Alternatively, selectorless RRAM that...
In this paper we present a 10-phases programmable clock generator for the application in control of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC), realized in the CMOS 130 nm technology. The circuit provides 10 clock signals on separate terminals (sections). The programmable feature means that we can program the number of clock phases which are cyclically repeated. The...
In this paper, a 10b 100-to-500 kS/s asynchronous SAR ADC is proposed and prototyped in 0.18 μm CMOS. The supply voltage is scaled down appropriately for different sampling speeds to minimize the power consumption. At a 0.5-V supply voltage and a 100 kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 56.35 dB and consumes 424 nW, resultin g in a figure of merit of 7.9 fJ/conversion-step...
In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded...
Analog-to-Digital Converts (ADC) are becoming essential to the function of ultra-high speed interconnects (IO) with complex modulation schemes, while at the same time reduction in supply voltage has negatively impacted the performance of such circuits. However the improvement in delay times and reduction in logic size has made time-based ADCs attractive. To accomplish this, a Voltage-to-Time Converter...
A comparator-based circuit that uses switched-capacitor charging replaces the op amp in the multiplying digital-to-analog converter (MDAC) of a low-voltage algorithmic ADC. MDAC output swing beyond Vdd allows greater than rail-to-rail ADC input range. At a supply voltage of 0.55 V, the ADC achieves 8.4 bit ENOB and 1.4 Vpp differential input range. It occupies 0.65 mm2 in 0.25-μm CMOS and dissipates...
Consider the structure of a self-oscillation power amplifier as a power line driver. Self-oscillation power amplifier was improved by the Class-D power amplifier. The traditional Class-D switching power amplifier is vulnerable to distortion limitation. Due to the non-linear continuous time nature of the self-oscillation, it possesses peculiar properties that enable the construction of a highly linear,...
The Internet of Things (IoT) became superior innovation area for nanoelectronic circuit design. This work is focused on a multi-modal power gating design approach for sensor node systems for IoT. Power gating is very efficient and flexible way for minimization of IoT CMOS circuits power consumption. However, only a very few papers suggesting multi-modal approach were published. Conventional power...
Filter-banks based on a gm-C topology are popular in acoustic sensor systems targeting spectral analysis. Their benefits lie in a very low power consumption and center-frequency scalability through gm-tuning to cover the audio frequency range. However the linear signal swing at the output of the filter is limited due to the inherent non-linearity of the input transistors in a differential pair. This...
The depth information is actively utilized for many applications such as mobile gesture user interface (UI). However, the previous stereo vision systems are unsuitable for the mobile gesture UI due to the long latency and the high-power consumption of external image sensor in embedded environments. In this paper, we propose a CMOS image sensor-based real-time stereo matching accelerator with low power...
Memristor-based arithmetic circuits promise new alternatives for their conventional CMOS-based peers due to memristor' s scalability and non-volatility features. In-memory memristor-based calculations become extensively attractive as it can be a solution to tackle memory bottleneck problems and also an ingredient for future beyond Von-Neumann computer architectures. In this paper material implication-based...
In this paper, a small-signal analysis of two SOI CMOS digitally tunable capacitor architectures intended for RF antenna tuning is provided. A mathematical model is derived and used to compare both architectures in terms of quality factor (Q-factor). The architecture with better Q-factor has been selected for implementation in a 130 nm SOI CMOS technology. To evaluate its potential for antenna aperture...
Internet-of-things applications require high energy-efficient ADC. Several SAR ADCs have been reported [1-2] with comparatively low FoMs by reducing the switching energy of the power hungry capacitor array. This paper proposes a shifted monotonic switching (SMS) scheme to achieve an average switching energy of 63.75CV2 with a reduction of 75%, 72%, and 73% compared to monotonic switching (MS), sub-ranging...
We present the design and implementation of a full adder circuit that exploits the natural flow of current through nanowires and More-than-Moore nano-devices in two dimensional crossbars. We evaluate the speed and energy efficiency of our design and compare it to equivalent one-bit adder designs using CMOS and nanoscale memristors. Our memristive full adder circuit has been shown to be an order of...
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