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In this work, a thermally stable air-bridged matrix (ABM) AlGaN/GaN high electron mobility transistor (HEMT) with micromachined diamondlke carbon (DLC)/Titanium thermal-distributed layers was demonstrated. After removing the Si substrate beneath the HEMT, the DLC/Ti heat dissipation layers were deposited on the backside of the HEMT, and a significant breakdown voltage improvement was observed. The...
We report on pn Ge solar cells grown on Ge substrates and transferred onto glass by wafer bonding. They perform similarly to cells on the native Ge substrate, whereas their energy conversion efficiency compares well with state-of-the-art stand alone Ge photovoltaic cells. We propose Germanium layer transfer and wafer bonding for the realization of effective multi-junction solar cells and versatile...
Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCut™ technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted.
Crystalline phase high-k films are promising gate stack structure for the advanced CMOS technology because they are thermodynamically stable and have higher dielectric constant when compared with amorphous phase high-k films. A disadvantage of crystalline high-k films, however, is the large leakage current, which is sometimes caused by grain boundaries and non-crystallized region in ultra-thin crystalline...
In order to compare antireflective characteristics between square pillar and columned sub-wavelength structures (SWSs), the relationships between diffraction efficiency and major structural parameters were examined by rigorous coupled-wave analysis (RCWA) on Ge substrate. The results showed square pillar and columned SWSs all had a good antireflective property; Filling factor and structural depth...
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials with Si can provide a variety of More-than-Moore and Beyond CMOS applications, where various III-V/Ge functional devices can be co-integrated. In this presentation, we review...
A capacitive sensor readout circuit on glass substrate for touch panel applications has been designed and fabricated in a 3-μm low temperature poly-silicon (LTPS) technology. In this work, the small voltage difference from capacitance change due to the touch event on panel is amplified by the switch-capacitor (SC) technique. In order to reduce the effect from device characteristic variation in LTPS...
We demonstrate selectively-grown GaAs nano/micro structures on silicon substrates by molecular beam epitaxy. Hexagonal or rectangular shaped GaAs crystals, depending on the orientation of the silicon substrate, were formed inside the silicon-dioxide-masked nanoholes at 630°C. Clear facets, which are the low-energy {011} planes, indicate single-crystalline nature of the growth. GaAs/InAs/GaAs structure...
In this study, the comparison of methods of improving electro-physical properties of silicon dioxide (SiO2) by means of silicon substrates fluorination in CF4 in PECVD and RIE reactors, prior to oxide deposition, has been performed. The results proved that, in general, fluorination in RIE is superior to the fluorination in PECVD reactor. The observed effects have been referred to the obtained changes...
While crystalline silicon FET's are the key enablers for the integrated circuit field, amorphous silicon thin film transistors are the key semiconductor of the large-area electronics field, also known as “macroelectronics.” This talk reviews the basic properties of amorphous silicon, and then outlines research trends, driven in large part by new applications. These trends include increased performance,...
Al/SiO2/pp+-Si metal-insulator-semiconductor (MIS) solar cell device was simulated using a comprehensive numerical model. The semiconductor layer consists of p-type Si epitaxial layer (base) which is deposited on p+-Si(001) substrate. The doping profile in the base layer was chosen to be arbitrary with different doping gradients. The effect of doping profile in the base layer and substrate was studied...
We present a study of Ti implanted Si layers with doses in the 1013-1016 cm-2 range that have been subsequently Pulsed-Laser Melted (PLM) at 0.8 J/cm-2. Recently, we have associated a rectifying electrical behavior found between the Ti implanted Si layers and the underlying substrate to the Intermediate Band (IB) formation in the Ti implanted Si layers with the highest doses. We analyze by means of...
In order to fulfill the stringent requirements for ultra-shallow junction formation and proper defect removal needed for future Si devices, molecular and cold implants have arisen as new technological strategies for dopant incorporation. In this work we have used different atomistic simulation techniques within a multiscale scheme to study the phenomena governing the damage generation in these types...
It is well known the gate dielectric conduction behaviour in high-k based MIS structures is usually dominated by more than one transport mechanism. In this work, results of the electrical performance of MIS structures on n- and p-Si using Al2O3, HfO2, and nanolaminated 10 nm-thick layers as gate insulators are reported. Clearly, different conduction mechanisms were observed depending on the applied...
This paper investigates the various effects that affect the ID-VDS characteristics in a strained-Si over SiGe NMOSFETs. The modeling is done keeping the BSIM4 parameters as the reference. The model thus developed showed precise agreement with the experimental data. It is observed that mobility in strained silicon increases and thereby enhancing current. Bandgap is affected to a lesser extent, but...
This study presents a novel design and fabrication process to realize a miniature polymer ball bearing slide table (slider) with long linear travel range. The linear slide table consists of a pair of V-shape silicon (111) crystal plane rails, and a suspended slider supported by four polymer ball bearings. The ball-housing on slider is also designed to confine the bearing. The slider, rails, and ball-housings...
We have developed and characterized a novel 3D flexible parylene-based microelectrode array (MEA) with silicon tips, which combines advantages of the rigid 3d electrode and the flexible substrate. The impedance of solid 3D MEA in PBS solution is smaller than that of the planar and hollow 3D MEA. Further tests indicate that the solid 3D MEA has better penetrating performance, and retains previous structure...
This work demonstrates the application of pulsed-laser processing for sealing release holes in silicon membranes. Holes in the membrane are sealed without deposition, similar to the silicon surface migration sealing process. In contrast to the 1100°C furnace anneal required for the migration process, the pulsed-laser process localizes the heat to the top few microns of the substrate, with the bulk...
We report a novel microfluidic surface-enhanced Raman scattering (SERS) device, which is achieved by bonding a polydimethylsiloxane cap with a microchannel structure onto an SERS-active substrate composed of noble-metal covered silicon nanopillar forests. The silicon nanopillar forests are fabricated by using nanomaterial dots, which are introduced in oxygen-plasma bombardment of photoresist, as etching...
We characterize the microwave loss in coplanar waveguides (CPWs) on AlGaN/GaN HEMT buffer layers on high-resistivity silicon (HR-Si) substrates, up to 110 GHz. To our knowledge, this is the first broadband characterization of CPWs on GaN-on-Si. Conventional CPWs on commercially available AlGaN/GaN on HR-Si HEMT layers show a loss as low as 0.8 dB/mm at 110 GHz. Losses are further reduced by etching...
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