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Reference oscillators are crucial hardware components of radio-frequency receiver circuits, as their performance directly affects the system performance. Especially in GHz applications, such as 4G/5G mobile communications, a low error-vector magnitude is required, which is strongly influenced by the phase noise of the reference oscillator. This paper reports the results of the design, simulation,...
In this work, a high voltage (HV) galvanically isolated chip-to-chip communication circuit utilizing laterally coupled resonators is reported. The adjacently placed resonators provide high voltage galvanic isolation (GI) using horizontal space between resonators filled with oxide, which minimizes the need for thick inter-metal dielectrics. A previously unexplored application for lateral coupling is...
A low-power multi-standard transceiver in CMOS 28 nm is presented. The transceiver can be configured to cover the range from 5 Gbps to 28.2 Gbps. Both transmitter and receiver use a supply of 0.92 V. Transmitter uses a 3-tap Finite Impulse Response (FIR) filter and receiver uses a 3-tap analog FIR and 2-tap unrolled Decision Feedback Equalizer (DFE). The entire transceiver uses single level 0.92 V...
Introduction. Fast CMOS ECL interfaces offer important savings in off-chip delays for high speed CMOS SRAM, especially for sub-10 ns accesses in high speed large system applications. Asynchronous CMOS differential amplifier circuits in a 1 μm 5V technology [1] can meet the joint requirement of high speed and light tolerances needed for ECL receivers [2J.
Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here we examine 25 Gb/s applications in the context of integrated transistor performance and demonstrate a 4λ×25 Gb/s reference design.
We demonstrate an optical link operating in indoor ambient lighting conditions using a CMOS single photon avalanche diode (SPAD) optical receiver and a RGB light emitting diode (LED). The high sensitivity of the SPAD receiver allows the link to operate at 2 m distance at a total 60 Mb/s and bit error rate (BER) of 1×10−3 without lensing. The transmitter implements color shift keying (CSK) using a...
A low complexity high speed generalised space shift keying (GSSK) visible light communication (VLC) link is investigated. A 2 × 2 Gallium Nitride (GaN) micro-LED array is used as transmitter and a complementary metal-oxide-semiconductor (CMOS) avalanche photo-diode (APD) array working as receiver. A bit error ratio (BER) of 2 × 10−4 up to a data rate of 320 Mbits/s is achieved which allows for error-free...
This work demonstrates a fully integrated 24 GHz CMOS receiver for high gain and wireless sensor network. The receiver incorporates a low noise amplifier, double-balanced mixer and an active balun for single to differential. This mixer designs with active load to decrease power dissipation. To increase mixer gain, an inductor is added to eliminate parasitic capacitances at the load of input transistor...
This paper presents a dual path Nuclear Magnetic Resonance (NMR) receiver dedicated to low cost NMR bio-molecular spectroscopy. Herein we present the design and implementation of CMOS based NMR receiver consisting of an integrated circuit (IC) incorporated with four mini-Coils for NMR exciting and recording purposes. The proposed 21 MHz CMOS receiver consists of differential low-noise amplifiers (LNAs),...
An improved architecture of an active quasi-circulator (QC) is proposed for monostatic FMCW automotive radars. Special attention is paid on the receiver noise figure (NF) performance as well as high transmit (TX) to receive (RX) signal isolation. The high TX/RX isolation is achieved by using a W-band CMOS based impedance tuner acting as a leakage canceler. Also process variation as well as antenna...
Optical receiver front-ends of varying technologies and packaging techniques are designed and compared. A 25 Gb/s monolithically integrated CMOS receiver consumes six times less power and four times less footprint than a discrete receiver.
A reconfigurable IF receiver supporting intra-band non-contiguous carrier aggregation is proposed. By utilizing the harmonic rejection (HR) mixer with 12-phase LOs and phase-shift-adding configuration, the IF receiver could eliminate the channel interferences, which is robust to the mismatch. The IF receiver has been implemented in 65nm CMOS, and the simulate d results show that the interference between...
Reaching a power efficiency of 1mW/Gb/s has proven difficult for wireline transceivers operating at tens of gigabits per second. At 40Gb/s, recent receivers consume from 150mW [1] to 1W [2]. This paper describes a receiver that achieves a tenfold reduction in power and an efficiency of 0.35mW/Gb/s.
The demand for energy-efficient I/O link transceivers operating at raw data-rates in the tens of Gb/s continues to fuel innovation in the field of wireline communication [1]. Receiving equalizers under one pJ/b are sought for chip-to-chip and chip-to-module links designed to operate across short-reach copper channels. Standards such as CEI-28G-VSR suit chip-to-module communication at raw data rates...
This paper presents the design of a fully integrated CMOS 4-channel phased-array receiver for 10.5–14.5 GHz telecom infrastructure, microwave link and radar applications. The phased-array is built using 0.13μm CMOS, and has a gain of 24.5 dB at 12.5 GHz, an input IIP3 of −7.3 dBm, a NF of 4.8 dB and the RMS phase error is 3o. The chip occupies an area of 2.9×3.2mm with a total power consumption of...
High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a die to achieve upward or downward scalability, or connecting to an off-chip SerDes or optics engine. Each of these in-package applications typically...
As CMOS devices continue to scale down in voltage and area, digital-based high-speed serial I/Os [1] become increasingly competitive with analog-based designs [2,3]. In addition to offering the PVT-independent performance of digital functions and superior power and area scaling to future technology nodes, digital-based I/Os can support advanced line modulation techniques that will become necessary...
Multilevel modulation formats, such as PAM-4, have been introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance for such systems to compensate for the severe channel impairment as the data rate continues to increase.
With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1–3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with...
A hash map implementation of the link analysis technique for obtaining jitter is proposed, under non-linear receiver conditions. The jitter PDF obtained from the link analysis, which typically assumes an LTI system, is passed through the I/O non-linear CMOS receiver voltage characteristics, obtaining the final jitter distribution. Simulations show promising results.
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