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We present a digital system for measurement of neutron spectra in mixed gamma-neutron fields. The signal from a standard scintillation detector is sampled at rate up to 1 GHz, using 12-bit analog-to-digital converters. First stage of the signal processing is performed on a Virtex 6 FPGA and partial results are streamed through a fast Ethernet link to a computer, where the final processing takes place...
Penetration levels of solar photovoltaic (PV) generation on the electric grid have increased in recent years. In the past, most PV installations have not included grid-support functionalities. But today, standards such as the upcoming revisions to IEEE 1547 recommend grid support and anti-islanding functions-including volt-var, frequency-watt, volt-watt, frequency/voltage ride-through, and other inverter...
Recently, a new lightweight block cipher, SKINNY, has been proposed by Beierle et al. in Annual Cryptology Conference 2016. This paper presents an area-efficient FPGA implementation of SKINNY block cipher. In this paper, a new column-serial structure is proposed to speed up SKINNY without compromising its area cost, and the implementation of SKINNY S-box is optimized by utilizing FPGA embedded dual-port...
It is costly to have a conventional three phase electricity supply system to service sparsely-populated rural areas. As a solution, the single wire earth return (SWER) network is widely used which has only one overhead conductor delivering power and the ground is used for the return path. This paper presents an on-line monitoring system, currently under development, to provide real-time power quality...
The quality of TRNG designs mainly depends on the grade of the noise source from which the entropy will be harvested to extract randomness. Especially for purely digital noise sources suitable for FPGA implementations the use of Ring Oscillators is suggested in many scientific publications. Standard Ring Oscillator based noise sources however have earned some criticism regarding the amount of entropy...
Given the recent difficulty in continuing the classic CMOS manufacturing density and power scaling curves, also known as Moore's Law and Dennard Scaling, respectively, we find that modern complex system architectures are increasingly relying upon accelerators in order to optimize the placement of specific computational workloads. In addition, large-scale computing infrastructures utilized in HPC,...
Advanced Driver Assistance System is a growing trend in automotive industry that integrates multiple discreet components to create system level solution. A typical ADAS system in an automobile has single or multiple radar chips to transmit and receive electromagnetic waves and a microcontroller to process received data that is used for assisting driver in decision making. Radar chip and microcontroller...
The P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture...
A problem-oriented processor on the basis FPGA for high-precision calculations in floating-point formats (64-, 80-, 128-bit) for solving poorly conditioned systems of linear algebraic equations by the Gauss method was developed.
It is important to allow the test engineer great flexibility when developing a test program. Highly skilled test engineers desire flexibility and different hardware platforms to test a Unit Under Test (UUT). In the past, the engineer was told to use specific test equipment and not provided with the option to program an instrument to their specific test and diagnostic plans. Being stuck in a rut on...
Digital ultrasound probes include the entire analog frontend in their enclosing and are equipped with a standard digital link. This enables to build very cost-effective ultrasound systems as they can be simply connected to a commodity device, such as a desktop PC, tablet or smartphone, running an ultrasound imaging application. Up to now, digital probes have been mainly demonstrated for low-end ultrasound...
High-level synthesis is increasingly being used to automatically translate existing software algorithms into hardware quickly and efficiently. Typically, the circuits created by HLS are implemented on Field-Programmable Gate Arrays (FPGAs). While the fine-grained architecture of an FPGA is well suited for general circuit implementation, it can result in excessive routing resource utilization for larger...
In this work, we present a modular software subsystem that exposes a set of APIs for supporting the automation of a set of design choices in the synthesis of a hardware accelerator by a proprietary FPGA toolchain. We model the subsystem around Vivado, Xilinx's proprietary FPGA toolchain, in order to provide a finer grained control on the toolchain's features with respect to the standard .tcl interface...
The paper discusses the application of System on Chip devices for processing Megapixel video streams. The domain of image processing using high resolution images is very demanding in the scope of calculating power and frequently exploits special processing hardware. The progress of integration technology brings about SoC which are capable of meeting such processing demands. Characteristics of FPGA...
Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits...
This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The advancements happening in VLSI technology day by day have made chip testing more complicated. This has paved way for the increased popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows self testing of...
This paper describe the implementation of a lock-in amplifier (LIA) which conforms to the AXI standard for on-chip communication. The design and implementation is based on the Zynq field programmable gate array (FPGA) present in the open-source instrument RedPitaya. The designed architecture is a mixed solution between VHDL hardware modules and software modules, running within an ARM CPU. General...
Digital video compression techniques have an important role that makes transmission and storage of multimedia content in bandwidth and storage space limited environment efficient. This paper describes 3D video coding using FPGA encoder architecture for newer and more reliable multimedia technologies to drive the industry to improve services in the field of entertainment marketing, to encourage the...
Coarse-grained reconfigurable arrays (CGRAs) are a style of programmable logic device situated between FPGAs and custom ASICs on the spectrum of programmability, performance, power and cost. CGRAs have been proposed by both academia and industry; however, prior works have been mainly self-contained without broad architectural exploration and comparisons with competing CGRAs. We present CGRA-ME - a...
Field Programmable Gate Array (FPGA) system is widely used in deep learning application and cloud system for acceleration. Quality and reliability of IP block is essential to the successful development of today's complex hardware acceleration design. In this paper, we discuss the important issues of quality and reliability of digital soft IP, and propose a qualification measurement system that can...
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