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Routing algorithms can improve network performance by maximizing routing adaptiveness but can be problematic in the presence of endpoint congestion. Tree-saturation is a well-known behavior caused by endpoint congestion. Adaptive routing can, however, spread the congestion and result in thick branches of the congestion tree — creating Head-of-Line (HoL) blocking and degrading performance. In this...
Finite State Machines (FSM) are widely used computation models for many application domains. These embarrassingly sequential applications with irregular memory access patterns perform poorly on conventional von-Neumann architectures. The Micron Automata Processor (AP) is an in-situ memory-based computational architecture that accelerates non-deterministic finite automata (NFA) processing in hardware...
Software Defined Networking (SDN) is fast gaining acceptance as a networking architecture, which simplifies network management, by separating the control plane from the data plane. Edge-Core SDN is an extended SDN architecture which divides the underlying network into edge and core components. This decouples the edge switch requirements from the network core switch behaviour. When the number of networking...
Recently, the SDN paradigm, which splits the control and data planes, initially defined for wired networks, has been considered as a solution for the management of WSNs (Wireless Sensor Networks). However, the adoption of OpenFlow protocol, the most widely deployed SDN standard, directly into the WSNs may require novel / customized hardware or incur significant signaling overhead. This paper proposes...
Synthesis and implementation are two fundamental steps of the hardware design. Mountains of work in this area synthesize and implement your design from Hardware Description Language (HDL) description to the target FPGA device. We present ISE plus Customized P&R, a tool-chain converting Verilog designs into XDL that contains Xilinx FPGA implement modules. A key aspect of this tool-chain is that...
Load balancing and energy conservation techniques are one of the important constraints in the design of in wireless sensor network (WSN). Usually, clustering technique helps the network in the minimum utilization of energy that results in enhancing network lifetime. Moreover, various nodes in the multihop network that are near to the base station drain their battery very quickly thus result in creating...
As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
E-health is one of the domains which will need more and more IoT solutions in the future, as it requires short delays for life-dependency situations and safe local storage spaces for privacy matters. The emergency context demands efficient communication and computing capacities, and the cloud vision as well as traditional TCP/IP way of communication cannot really suit these requirements. New approaches...
Multi-level clustering offers the scalability that is essential to large-scale ad hoc and sensor networks in addition to supporting energy-efficient strategies for gathering data. The optimality of a multi-level network largely depends on two design variables: 1) The number of levels, and 2) The number of nodes operating at each level. We characterize these variables within a multi-hop, multi-level...
Software Defined Networks split the data plane from the control plane. They can be used in wireless networks and will bring flexibility, less interference, simple management, less energy consumption and load balancing. They can also improve service quality, handover and mobility between different service providers. In previous methods, when link states were changed the controller deleted the stored...
Software-Defined Networking (SDN) is an innovational network architecture introduced a couple of years ago. It gives network administrators the ability to directly control the whole network by programming on a centralized controller, without manually configure each device. However, new security challenges come out with SDN development. One significant challenge is to design a secure firewall specifically...
Deep Convolutional Neural Networks (CNNs) achieve substantial improvements in face detection in the wild. Classical CNN-based face detection methods simply stack successive layers of filters where an input sample should pass through all layers before reaching a face/non-face decision. Inspired by the fact that for face detection, filters in deeper layers can discriminate between difficult face/non-face...
Research tools targeting commercial FPGAs have most commonly been based on the Xilinx Design Language (XDL). Vivado, however, does not support XDL, preventing similar tools from being created for next-generation devices. Instead, Vivado includes a Tcl interface that exposes Xilinx's internal design and device data structures. Considerable challenges still remain to users attempting to leverage this...
The architecture of the Microsoft Catapult II cloud places the accelerator (FPGA) as a bump-in-the-wire on the way to the network and thus promises a dramatic reduction in latency as layers of hardware and software are avoided. We demonstrate this capability with an implementation of the 3D FFT. Next we examine phased application elasticity, i.e., the use of a reduced set of nodes for some phases...
CPU-GPU heterogeneous systems are emerging are emerging as architectures of choice for high-performance energy-efficient computing. Designing on-chip interconnects for such systems is challenging: CPUs typically benefit greatly from optimizations that reduce latency, but rarely saturate bandwidth or queueing resources. In contrast, GPUs generate intense traffic that produces local congestion, harming...
Network-on-Chip (NoC) is a nascent approach for reducing the communication bottleneck of multicore System-on-Chip (SoC). As the number of cores are increasing on SoC due to high performance demand of the consumer electronics and processing systems like servers, the low power and low latency NoC is required. Topologies are one of the most important parts of a NoC design, with considering the performance...
Information Centric Networking (ICN) is future Internet architecture for distribution of the contents which are location independent and are cached in the ICN nodes, making them efficient for distribution and retrieval. ICN architecture is based on new protocols for unique naming and transferring of data objects over the network. Its focus is on delivery of data objects to the end user rather than...
Healthcare information is growing significantly and using big data solutions like NoSQL databases for huge volume of data and data processing distribution are urgency. Moreover, various standards in electronic health record (EHR) employe an online transaction processing (OLTP) database that interacts with family health team to integrate all patient's clinical data from birth to death. In contrast,...
Routing in Delay-/Disruption-Tolerant Networking (DTN) requires specific solutions as link impairments prevent the use of ordinary Internet algorithms, based on a timely dissemination of network topology information. Among DTN routing algorithms there is a dichotomy between opportunistic and deterministic (scheduled) solutions. The former are numerous and apply to terrestrial environments; CGR is...
The scalable and massively parallel computing systems composed of many processors, which are connected on chips that will become more and more complex and unreliable. This paper presents a bio-inspired error tolerance framework and three design principles based on the Autonomous Error Tolerant (AET) architecture. A nearby error perception mechanism is carefully designed to detect faults and an initiative...
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