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In accordance with the resent advancement in Internet of Things (IoT), the needs for IoT experiment platform have been ever increasing. IoT system consists of various technologies such as networking, sensor controller, edge-side computing, server-side big data collections, analysis and their visualizations. An experimental environment that can handle the development and experiments of such an IoT...
Our society relies upon information processing at a scale never seen before in human history. We are indeed experiencing an exponential growth in processing demand, as more and more applications in the most disparate domains emerge. While continuous improvements in the manufacturing processes of microprocessors has been able so far to mitigate the ecological and economical costs this trend imposes,...
In this paper, the implementation of the K-means clustering algorithm on a Hadoop cluster with FPGA-based hardware accelerators is presented. The proposed design follows MapReduce programming model and uses Hadoop distribution file system (HDFS) for storing large dataset. The proposed FPGA-based hardware accelerator for speed up the K-means clustering algorithm is implemented on Xilinx VC707 evaluation...
This work presents the proof of concept implementation for the first hardware-based design of Moving Target Defense over IPv6 (MT6D) in full Register Transfer Level (RTL) logic, with future sights on an embedded Application-Specified Integrated Circuit (ASIC) implementation. Contributions are an IEEE 802.3 Ethernet stream-based in-line network packet processor with a specialized Complex Instruction...
In this work, a novel method Reduced CORDIC Based Logarithm Converter (RCBLC) is introduced for computing the specific-based logarithm of the binary values, and then the hardware architecture of RCBLC based on FPGA is analyzed in detail. Hardware architecture of RCBLC is implemented such that it enables logarithm conversion with both high output bit-sensitivity and low resource utilization. In addition...
Reservoir Computing is a bio-inspired computing paradigm for processing time dependent signals. It can be easily implemented in hardware. The performance of these analogue devices matches digital algorithms on a series of benchmark tasks. Their capacities could be extended by feeding the output signal back into the reservoir, which would allow them to be applied to various signal generation tasks...
With the increase of technological developments, the speed limit of the processors that have emerged has accelerated the reduction of nanotechnological solutions of transistors into atomic dimensions from nanometers. Physical systems in which stochastic computation is critical instead of deterministic computation by taking action from atomic behavior are discussed. For this reason, as an interdisciplinary...
An Arithmetic logic Unit (ALU) is used in arithmetic, logical function in all processor. It is also an important subsystem in digital system design. Arithmetic Logic Unit (ALU) is one of the most important components of any system and is used in many appliances like calculators, cell phones, and computers. A 32-bit ALU was designed using Verilog HDL with the logical gates such as AND and OR for each...
Link Training and Status State Machine (LTSSM) is a state machine in Universal Serial Bus (USB) which is defined for link connectivity and the link power management. LTSSM consists of 12 distinct states which are characterized depending on their functionalities. This paper reveals the FPGA implementation of LTSSM providing with USB 3.1 specifications with a support of USB 3.0 and 2.0 specifications...
Significant barriers to real time face detection have been the complexity of computation kernels, minimal costand superior accuracy requirements for both software and hardware implementation based on traditional high performance computing. It is desirable to develop variable precision face detection block for high dynamic range applications including night vision and infrared face detection applications...
Hardware Intelligence is an attractive concept that has the potential to make electronic, industrial and reliability-oriented applications efficiently optimized. This work investigates different frameworks and analyzes their challenges. Hardware automation faces different challenges like scalability, overhead, testability as well as goal definition. For better classification, hardware systems are...
This paper presents the design of pipelined IEEE 754-2008 decimal floating-point (DFP) multipliers targeting FPGAs. A key component of the architecture is the fixed-point multiplier function which impacts the overall performance and area utilization. In this paper, we propose a new method to realize this operation by carefully organizing the partial products and developing an algorithm for binary-decimal...
A novel high performance pipelined implementation architecture for user-defined floating-point complex division is presented. The major part of the proposed algorithm is derived from conventional Goldschmidt division algorithm. This paper first describes related user-defined floating-point arithmetic based on FPGA. Then the core of the complex division: (A+jC)/B is implemented based on the proposed...
Multipartite table methods offer a high speed, low area implementation of commonly used functions for up to 24 bits of accuracy. Currently the parameters which dictate the configuration of these tables are chosen using a worst-case rounding approximation scheme which often generates sub-optimal results. This paper will show that it is possible to perform a full exhaustive search to find the minimum...
Reliable storage is central component of data centers that support private or public cloud. Erasure coding has becoming increasingly popular alternative to replication for its capability in substantially cutting disk cost while delivering the same reliability. This paper reports the comprehensive results of using FPGA for accelerating erasure encoding and decoding algorithms. In particular, to accomplish...
The questions of further implementation of the operating system software means for the FPGA-based self-configurable computer systems support discussed in the paper. An approach for the FPGA-based self-configurable computer systems support using Unix-like OS presented. According proposed approach in the self-configurable computer systems (SCCS) the labor-intensive and time-consuming works of tasks...
The paper proposes a new approach for FPGA reconfiguration based on usage of the open-source synthesis and place-and-route tools. The well-known partial reconfiguration technologies assume pre-compilation of all required FPGA configurations by the designer. In autonomous intelligent control systems it can become quite a strong limitation, due to control law couldn't be changed on-board without using...
With the recent explosive growth of data in the real world, data mining techniques to obtain characteristics and knowledge from big data attract more attention. This paper focuses on a method to detect outliers in streaming data, and proposes a fast FPGA implementation of outlier detection based on the Mahalanobis distance. The proposed circuit is fully pipelined, and in every clock cycle, a given...
The aim of this paper is to present a new platform for evaluating impact of faults on electro-mechanical systems based on SRAM-based FPGAs. Functional verification together with the fault injector serve as a tool for the fault tolerance evaluation. The article demonstrates the use of the verification environment for evaluating impacts of faults in electro-mechanical systems. Our system consists of...
Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation...
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