The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running...
The Parity Generators and checkers are crucial block in Central Processing Unit especially in the process of Error Detection and correction during data transmission. In this work, the three-bit Quantum Cellular Automata (QCA) even parity generator have been proposed using Layered T AND and OR Gate. The proposed comparator layout needs 9.02% less effective area compared to the best reported design...
Encoders using generator polynomials and linear-feedback shift registers are the key parts of communication technologies widely used in most of today's integrated as well as field systems. This paper presents a detailed comparison of three ways of implementation of configurable encoders arranged in PENCA and implemented in Xilinx and Altera FPGAs.
This paper presents a time-delay system which originally has chaotic behavior, yet lost that dynamic due to finite quantization levels of state variable representation. One method to overcome this destructive effect of digitalization is engaging a time-varying delay amount which is studied in this paper. Based on this system, random number generator (RNG) topologies are demonstrated with better throughput...
Stochastic circuits (SCs) offer tremendous area and power-consumption benefits at the expense of computational inaccuracies. They require random num-ber sources (RNSs) to implement stochastic number generators (SNGs) for all of their inputs. It is common for an SC to have a large number of primary and auxiliary inputs. Often the associated SNGs take up as much as 80% of the entire circuit area, so...
True Random Number Generator (TRNG) occupies a commendable position in various information security applications. Random numbers are the one which need to possess the properties of uniform distribution and statically independent. Diffused bit Generator (DBG) is a reliable entropy source and core component to produce the sequence of random bits. The bits emanating from DBG is usually further sampled...
True random numbers have a fair role in modern digital transactions. In order to achieve secured authentication, true random numbers are generated as security keys which are highly unpredictable and non-repetitive. True random number generators are used mainly in the field of cryptography to generate random cryptographic keys for secure data transmission. The proposed work aims at the generation of...
Polish power system is facing increase in demand for energy relative to stagnation in development of installed power capacity, caused mainly by CO2 emissions reduction policy. Therefore, investments resulting with increase of energy efficiency, hence lower emissions relative to produced power are becoming more important. Recently much greater attention is diverted to cogeneration of heat and electric...
A major limitation in authenticating passive and remotely powered sensors, tags and cards (for e.g. radio-frequency identification tags or credit cards) is that these devices do not have access to a continuously running system clock. This obviates the use of SecureID type authentication techniques involving random keys and tokens that need to be periodically generated and synchronized. In this paper...
Arithmetic Logic Unit plays a vital role in the central processing unit of the computer system. Addition is considered to be a primary part in the ALU. Power and speed are the major parameters to be kept in mind for designing an adder. Because of carry propagation, complexity and delay gets introduced in the adder circuit due to which addition, subtraction and multiplication obtains delay in the Arithmetic...
Entity linking is the task of identifying entities like people and places in textual data and linking them to corresponding entities in a knowledge base. In this paper we solve a visual equivalent of this task called visual entity linking. The goal is to link regions of images to corresponding entities in knowledge bases. Visual entity linking will enable computers to better understand visual content...
Due to globalization of IC, hardware is defenseless to new sorts of assaults, for example, counterfeiting, figuring out and IP piracy. Logic locking technique is used for the hardware security. Logic locking conceals the functionality and implementation of a design by inserting additional gates into the original design. The gates inserted for the locking are called key-gates. To display its correct...
This paper develops a model for Wells turbine using Xilinx system generator (XSG)toolbox of Matlab. The Wells turbine is very popular in oscillating water column (OWC) wave energy converters. Mostly, the turbine behavior is emulated in a controlled DC or AC motor coupled with a generator. Therefore, it is required to model the OWC and Wells turbine in real time software like XSG. It generates the...
Energy efficiency presents a significant challenge for stochastic computing (SC) due to the long random binary bit streams required for accurate computation. In this paper, a type of low discrepancy (LD) sequences, the Sobol sequence, is considered for energy-efficient implementations of SC circuits. The use of Sobol sequences improves the output accuracy of a stochastic circuit with a reduced sequence...
Current techniques for formally verifying circuits implemented in Galois field (GF) arithmetic are limited to those with a known irreducible polynomial P(x). This paper presents a computer algebra based technique that extracts the irreducible polynomial P(x) used in the implementation of a multiplier in GF(2m). The method is based on first extracting a unique polynomial in Galois field of each output...
This paper addresses the problem of unreliable internet access in Intelligent Transportation System through a secure acknowledgement routing protocol. Identity-Based Digital Signature scheme is preferred over traditional certificate based Digital Signature due to underlying resource constrained Vehicular Ad-Hoc Network. Verifiable hash chains paired with IBS are used in the protocol to increase the...
Reliability models of doubled systems with hot and cold redundancy are suggested. The switching device can makes type I and II errors in these systems. Dynamic fault trees and Markov models are used for reliability characteristics determination.
In the Modern computers for performing the operationof ALU (Arithmetic Logic Unit) like Addition, Subtraction, different types of adders are using for achieving low delay and fastoutput. QSD numbers are using for giving the carry-free additionso that ALU operations can perform in low delay and speed of themodern computer can increase. In the modern digital system fastadder, Subtraction can perform...
Non-linear chaos is a property of equations, cauterized by non-periodicity, the high sensitivity to initial conditions and his control parameters, ability to reciprocal synchronization and unpredictability. The deterministic nature of the chaotic system can be used to generate a pseudorandom sequence for digital ciphering algorithms. This work presents a pseudo-random bit generator (PRBG), based on...
An adaptive inverter-based dead-time controller for synchronous DC-DC converter is proposed. With this controller, the switching time is precisely controlled and thus simultaneously eliminates the power losses caused by body-diode conduction, power-stage shoot-through current and inductor reverse current. A pair of inverters are used to replace the high speed comparators in this controller for even...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.