The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Now a day market demands compressed devices that operates on low voltage and causes less noise in the output. Advanced nano scale very large integrated circuits are facing significant timing closure challenges especially due to random on chip threshold voltage variations. Memristor can play an important role in improving the scalability and efficiency of existing memory technology. Accordingly this...
In this paper, we designed Schmitt trigger using CMOS low power design technique at 45nm technology. With the advancement of technology, different parameters have been calculated and analyzed to determine the performance of the circuit. With the change in technology, the aspect ratio of transistor sizing, variation in parameters also takes place. Different techniques are applied for the reduction...
This paper presents the design and analysis of a 2∶1 multiplexer. The conventional circuit of 2∶1 multiplexer(MUX) is used for the calculation of different parameters like power consumption, noise, delay, leakage power, etc. The multiplexer designed in this paper is suitable for low-power applications and works on very low supply voltage. Multiplexer is a digital circuit, it consists of 2N input and...
This paper presents a resistor-free self-regulating CMOS ring oscillator (RO) whose oscillation frequency is insensitive to supply noise variations. The proposed RO design achieves self-regulation by adopting a cross-coupled dual latch-based scheme; Proper custom device sizing of the cross-coupled latches can improve supply noise immunity and frequency stability compared to a simple inverter design...
This paper presents the design of a low leakage CMOS based switch mode power supply. The switch mode power supply converts the available deregulated A.C or D.C input supply to a regulated D.C output supply. This paper reviews the limitations of conventional linear regulated power supply and focuses on the advantages of switch mode power supply (SMPS) technique. The high frequency transformer used...
This paper compares two types of physical unclonable function (PUF) circuits in terms of reliability, mismatch-based PUF vs. physical-based PUF. Most previous PUF circuits utilize device mismatches for generating random responses. Although they have sufficient random features, there is a reliability issue that some portions of bits are changed over time during operation or under noisy environments...
This paper introduces a novel low-power Ion-Sensitive Field Effect Transistor (ISFET) readout configuration compatible with standard CMOS technology that utilizes chopping technique to reduce the 1/f noise and the offset of the readout circuitry. In addition, the proposed scheme tackles the well-known non-idealities of the ISFET such as the trapped charge and the long-term drift by using a resetting...
This paper presents a wireline receiver design of CMOS I/O at 10-Gb/s data rate. A power efficient continuous-time linear equalizer (CTLE) and 1-tap lookahead decision feedback equalizer (DFE) are designed and implemented in a 45 nm CMOS technology. The DFE employs a sampler including a current injection section that makes no use of summer as a separated block. In addition, cascode structure increases...
A Mixed-signal bio-potential signal interface is presented. It uses a feedback loop that acts like an adaptive notch filter to increase system immunity to power line interference. The proposed feedback loop automatically detects the frequency of power line interference without the need for a phase locked loop, it also exploits an optimized technique for frequency generation that minimizes digital...
This paper investigates an inductorless technique for bandwidth extension which uses local positive feedback in an optical receiver front-end based on an inverter-based transimpedance amplifier and Cherry-Hooper post-amplifiers. Small feedback inverters create negative resistance that boosts the output resistance of inverter-based amplifiers. Compared to a reference design having a TIA and a three-stage...
A 100 Gb/s transimpedance amplifier (TIA) for next generation optical communication adopts a diode-connected input-resistance-reduction architecture and is designed in 32 nm CMOS SOI technology. The proposed TIA design is based on a gm-boosted common-gate amplifier with a diode-connected current source and incorporates a single-to-differential signal conversion architecture. The input resistance of...
This paper presents an open loop readout circuit technique for capacitive inertial sensors using a charge balanced and ratiometric approach. The charge balance is achieved through a delta-sigma loop allowing for direct analog-to-digital conversion at comparatively lower power. Techniques for achieving differential implementation, noise and offset cancellation are also discussed in lieu of the limitations...
Analog error correction allows discrete-time continuous-alphabet signals to be protected against channel impairment without the need for a digital representation or digital circuit. This is a powerful way to distribute the representation of an analog value across multiple wires or multiple devices in a manner similar to how digital representations distribute bits across multiple wires and devices...
Chopper stabilization is the most widely used circuit technique to reduce the influence of the flicker noise in an amplifier. Recently, observation of /ƒ2 input-referred noise in the chopper amplifier with a high-impedance input source was reported. However, the mechanism of this /ƒ2 phenomenon has not been completely analyzed. This paper provides the complete analysis of the noise influence generated...
High density and high bit rate optical interconnects require higher level of integration and complexity. These solutions require circuits design techniques that result in low power and low crosstalk penalty which will be discussed in this paper.
This paper makes a review of main methods to improve the linearity of ADCs. Methods are collected in view of mainstream techniques. A model of redundant noise-shaping Pipelined Flash-SAR ADC is proposed, which is the combination of Flash, Pipeline, SAR and ΣΔ ADC, the effectiveness of the model is demonstrated by simulation. Also, application of dynamic element matching (DEM) linearization techniques...
A 410-GHz imager consisting of a 4th sub-harmonic mixer formed with an anti-parallel diode-connected NMOS transistor pair, and an on-chip antenna with 4.4-dB simulated gain is demonstrated in 65-nm CMOS. At −1.6-dBm power delivered to the LO input bond pad, the imager achieves 16.8-dB voltage conversion loss and 34.1-dB DSB noise figure. When the noise bandwidth is 1 kHz, sensitivity is −110 dBm,...
This paper presents a system consisting of an array of thin-film microphone channels on glass, which can be formed on large substrates. Each microphone channel consists of a polyvinylidene difluoride (PVDF) piezoelectric transducer as well as amplifier and scan circuits basedon amorphous-silicon (a-Si) thin-film transistors (TFTs). The scan circuits multiplex signals from multiple channels to a CMOS...
An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk)...
A 14b 750MS/s 21.1mW current steering digital-to-analog converter (DAC) is presented, which maintains <-168dBm/Hz noise spectral density beyond the Nyquist frequency to minimize TX leakage in SAW-less FDD LTE. A hybrid wideband R-2R LSB segmentation with an impedance attenuator minimizes glitch noise across process and temperature without requiring accurate scaling of switches and switch drivers...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.