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This paper deals with the implementation of low voltage, energy efficient and high speed 1-bit Full Adder (FA) cell in pass transistor (PT) logic by using 20 nm compact model parameters. The existing full adder with pass transistor logic suffers from a drawback of replication of full swing in sum and carry outputs and voltage step existed in both the outputs at low to high transition. These will be...
The VLSI architecture for the low power combined FM0 and Manchester encoder (SOLS) circuit using modified GDI has been proposed in this paper. Comparisons are made with existing architecture using general CMOS Logic. The power consumption and delay in this circuit are reduced. The working conditions for existing circuit for FMO/Manchester encoder and decoder using HCPM technique have also been modified...
BI-CMOS technology has allowed the implementation of a new type of gate array which is part ECL logic for high speed and part BiMOS logic for low power dissipation. Test circuits have been fabricated and show acceptable performance of ECL logic on the BiMOS process. Applications of a mixed technology gate array are discussed.
Many important fields for the application of semiconductor ICs (e.g. digital communication networks, factory automation, office automation) are governed by processing digital data streams. Often these data streams are split into parts, which are processed separately. Afterwards usually synchronization is necessary, because different latencies occur in each processing unit. A delay circuit, which is...
Recently, in the field of the nonvolatile memories, the demand for OTP-ROM (One Time Programmable-ROM) devices has been rapidly increasing. The OTP-ROM is an EPROM enclosed in a plastic package. From the market research, EPROMs are programmed only once in many cases. If an EPROM is enclosed in a more inexpensive plastic package rather than a package with a window for UV (Ultra-Violet) erasure, it...
Introduction. Fast CMOS ECL interfaces offer important savings in off-chip delays for high speed CMOS SRAM, especially for sub-10 ns accesses in high speed large system applications. Asynchronous CMOS differential amplifier circuits in a 1 μm 5V technology [1] can meet the joint requirement of high speed and light tolerances needed for ECL receivers [2J.
A high speed circuit with precharged technology is described, k 32-bit ALU which employs this technology has been designed. New ALU realized about 2.5 times faster speed than that of former one which was designed by poly-cell technology, A carry-propagation delay time by the carry-lookahead and the conditional-sum was 5.0ns, which is 3.6 times faster than that of poly-cell approach. This technology...
In the development of high density DRAMs such as 1 M bit or beyond, it will be increasingly important to achieve high speed, competitive to SRAMs, in addition to low cost per bit. Recently, BIPOLAR CMOS (BICMOS) technology has been proposed for achieving high speed and low power operation, especially SRAMs (1,2).
The conversion time for high-speed analog-to-digital converters is limited by the rate at which the internal comparator(s) can amplify small voltages 1 into logic levels. Several comparators have been designed with response times of less than 10 ns [1,2]. However, these circuits are usually fabricated with bipolar transistors.
This paper presents an implementation of a binary pulse-position modulator (2-PPM) for impulse-radio ultra-wideband (IR-UWB) systems, capable of producing an appropriate signal to drive the final output stage of an ultra narrow pulse generator. Compared to the usual circuits based on voltage-controlled delay lines, this novel scheme uses digital signal processing of the clock and data signals with...
A zero-crossing based amplifier whose power is scalable to a sampling frequency is presented. An inverter-based zero-crossing detector (ZCD) is proposed to consume no static power consumption compared with a conventional ZCD using a class-A based preamplifier. A common-mode feedback (CMFB) circuit is adopted to calibrate a variation of a ZCD threshold voltage due to supply voltage and temperature...
Many existing XOR-XNOR cells suffer from nonfull-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR-XNOR cell, is presented. Simulation results in 90-nm CMOS technology show that the proposed circuit has rail to rail outputs Also, we have gained 11%–51%, 2%–19% and 18%–52% improvement in delay, power consumption and power-delay product...
High speed silicon optical modulators must be compatible with CMOS drivers to reach their full potential for low cost and low power consumption. We designed a CMOS driver for a Mach-Zehnder modulator (MZM) that has been segmented to lower required voltage swings on a per segment basis and to increase the speed. Previous inductor-less drivers produced on the same process, IBM 130 nm CMOS, ran at 10...
Analog-to-Digital Converts (ADC) are becoming essential to the function of ultra-high speed interconnects (IO) with complex modulation schemes, while at the same time reduction in supply voltage has negatively impacted the performance of such circuits. However the improvement in delay times and reduction in logic size has made time-based ADCs attractive. To accomplish this, a Voltage-to-Time Converter...
Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing...
A wideband, CMOS current driver for bioimpedance measurement applications has been designed employing nonlinear feedback. With the introduction of phase compensation, the circuit is able to operate at frequencies higher than the pole frequency of the output transconductor with minimum phase delay. Moreover, it isolates the poles required for stability from the high frequency characteristics of the...
This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages...
This paper presents 3D IC design of a fully integrated four-phase buck converter. The control circuit was implemented in the TSMC 0.18μm CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8 & 3.3V process while the passive components were implemented in the tMt Glass Substrate Integrated Passive Device (IPD) Process, and then these two dies are stacked. Thus, a high output loading current can...
A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data...
A scalable 7.0-Gb/s/lane, 6-lane serial link transceiver for chip-to-chip NRZ data communication is described. Its serializing transmitter uses a new circuit topology, with data-controlled pulse generation followed by pulse-controlled serialization, and provides improved bandwidth and power efficiency with the elimination of on-chip NRZ signaling and retiming while preserving the bandwidth benefit...
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