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This paper describes an energy-efficient PAM-4 digital receiver based on sequence detection. This scheme takes advantage of the ISI in the channel to reconstruct the time domain 5-bit sequence including MSB and LSB. The architecture also enables built-in error correction with very low latency. This concept is demonstrated with prototype implemented in a 28nm FDSOI CMOS using only 18-data comparators...
Different neural network models have been proposed to design efficient associative memories like Hopfield networks, Boltzmann machines or Cogent confabulation. Compared to the classical models, Encoded Neural Network (ENN) is a recently introduced formalism with a proven higher efficiency. This model has been improved through different contributions like Clone-based ENN (CbNNs) or Sparse ENNs (S-ENNs)...
In this paper, the principle of normalized minimum-sum (NMS) polar decoding process is explored. It is demonstrated that with one properly chosen parameters for NMS algorithm, performances approach to that of the sum-product (SP) algorithm can be achieved. As well, the complexity reduction is realized by calculating a linear function instead of nonlinear function. Simulation results for successive...
This paper presents a solution for establishing communication with Icecast and Shoutcast audio broadcasting servers. Web radio station is implemented, which means that is possible to broadcast an audio content from the local computer through Shoutcast and Icecast servers. Also, audio player is implemented for both local files, as well as web radio using FFmpeg libraries for audio package manipulation...
We propose an underlay decode-and-forward cognitive (UDFC) scheme under joint effects of hardware impairments at secondary users and interference constraints at multi primary receivers. In this scheme, the transmit powers of a source node and relays are constrained by interference thresholds of primary receivers in which the best relay is selected has the highest decoding capacity from the source...
This paper focuses on low complexity architectures for check node processing in Non-Binary LDPC decoders. To be specific, we focus on Extended Min-Sum decoders and consider the state-of-the-art Forward-Backward and Syndrome-Based approaches. We recall the presorting technique that allows for significant complexity reduction at the Elementary Check Node level. The Extended-Forward architecture is then...
Reed-Solomon code or RS code is widely used for error corrections of data in transmission and storages. However, it is thought of as insecure for direct implementation in code-based cryptography due to plaintext-known attacks. In recent years, McEliece cryptosystem with enhanced public key security by generalized RS code and Goppa code are discussed for hardware implementation. In this work, from...
Low-density parity-check (LDPC) coded massive multiple-input and multiple-output (MIMO) scheme is getting increasingly popular and sophisticated in today's wireless communication systems, since it can highly improve the spectral efficiency, data rates, and error performance. In this paper, a novel iterative detection and decoding (IDD) method for LDPC-coded massive MIMO systems is proposed. Based...
Current multi-user detection scheme for sparse code multiple access (SCMA) is iterative message passing algorithm (MPA) in which the message update strategy is in a parallel manner. To take full advantage of MPA's feature of parallelism, this letter proposes a hardware implementation strategy of max-log MPA decoder used in SCMA systems with soft baseband, which is based on general-purpose computing...
In this paper we present a scalable multi-view video streaming system with client-side view interpolation. Most parts of the system have been shown to be able to perform in real-time, but never as a complete system. Even though our algorithms are not yet highly optimized, we show that running a complete multi-view streaming system video on consumer hardware is possible today. Since multi-view coding...
Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on...
In this contribution, we present a coverage driven functional verification environment based on the UVM framework and the System Verilog language to certify the operational correctness of the ECC error management logic used in volatile and nonvolatile memories. We apply this methodology to floatinggate nonvolatile memories for the embedded market, which requires a read error rate of 10−14. The proposed...
Model of Turbo-Product Codes decoder architecture and method for construction of Turbo-Product Codes decoder are proposed in the paper. The model describes decoder functioning taking into account limitations of hardware platform and proposes re-use of components in the decoding process. The method provides set of steps for decoder implementation. Field-Programmable Gate Arrays circuits are selected...
The degree to which Turbo-Code decoder architectures can be parallelized is constrained by requirements for flexibility with respect to code block sizes and code rates. At the same time throughput requirements are expected to increase by a factor of up to 20x for 5G networks, which are currently undergoing standardization. The limiting factors for the throughput of a Turbo-Code decoder are maximum...
In this paper, two novel hardware architectures based on tabled asymmetric numeral systems decoding algorithm are proposed. In the proposed architectures the decoding throughput is highly dependent on the how much the data is compressed at encoding time. The synthesis results presented here show that the throughput of the parallel architecture can reach up 200 MB/s. The benchmarks show that the parallel...
In this paper, a high speed digital excess loop delay (ELD) compensation scheme with hybrid thermometer coding is proposed. In this high speed compensation, the time constraint of the DAC feedback route is shifted to the one clock compensation path. Also, the method to deal with the signal overflows the quantizer's range is analyzed. Compared to other digital ELD compensations, this scheme features...
In this paper, iterative decoding using Belief Propagation λ-min decoding algorithm is considered. In this algorithm check nodes use only the λ lowest-magnitude messages thus simplifying the hardware complexity and reducing memory usage. A parallel-input architecture is proposed for the check node. We focus on the determination of the sought minima in a parallel fashion. Novel simplified circuits...
Belief propagation (BP) polar code decoder is well-studied from many aspects. This study proposes a hardware optimization to improve performance of polar BP decoder by modifying both processing element (PE) and early stopping criterion (ESC). PE is optimized by using high-speed parallel-prefix Ling adder instead of carry ripple adder and WIB ESC introduced in literature is optimized by removing unnecessary...
Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads...
LDPC still receives extensive attention in the field of channel coding because of its superior error correction performance, high throughput and low decoding complexity. Considering the poor adaptability and limited expansibility of traditional LDPC decoder, a design method of LLR-BP decoder based on adaptive code length is proposed. A partial parallel LDPC decoder structure is designed under the...
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