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Low-power equalization remains in high demand for wireline receivers operating at tens of gigabits per second in copper media. This paper presents a design incorporating a continuous-time linear equalizer and a two-tap half-rate/quarter-rate decision-feedback equalizer that exploits charge steering techniques to reduce the power consumption. Realized in 45 nm technology, the prototype draws 5.8 mW...
The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a greater challenge to reach the generally-accepted efficiency of 1mW/Gb/s. Prominent among the power-hungry receiver building blocks are the clock-and-data-recovery circuit, the deserializer,...
A half-rate clock and data recovery circuit and a deserializer employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz.
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