Search results for: Yuki Fukazawa
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Concurrency and Computation: Practice and Experience > 30 > 9 > n/a - n/a
Ineffective column‐directional cache memory access has become a bottleneck for efficient two‐dimensional (2‐D) data processing utilizing extended single instruction multiple data (SIMD) instructions. To solve this problem, we propose a cache memory with tile (column and row directions) and line (row direction) accessibility for efficient 2‐D data processing. 2‐D data access to the proposed cache memory...
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A multi-core processor is widely used to achieve both high performance and low energy consumption. However, verification of a multi-core processor is more difficult than that of single-core processor. Because multi-core processor has large and complex circuits, and special mechanisms such as a cache coherency mechanism also increases complexity. In general, design flow of a processor include such...
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Ineffective data access of cache memory has become a bottleneck for efficient 2-dimensional (2-D) data processing, such as image processing and matrix multiplication. To solve this problem, a cache memory with both unit tile and unit line accessibility, based on a 4-level Z-order tiling layout is proposed. Conventional raster scan order access to this layout is enabled via a hardware-based address...
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Ineffective data access of cache memories becomes a bottleneck for efficient 2-dimensional(2-D) data processing such as image processing and matrix multiplication. In order to solve this problem, a cache memory with both unit tile and unit line accessibility, based on 4-level Z-order tiling layout is proposed. Conventional raster scan order access to this layout is enabled by a hardware-base address...
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Even high-performance general purpose processors are not sufficient for speedy motion estimation (ME), though they support some SIMD instructions for ME. In this paper, we propose a SIMD-based general-purpose-oriented datapath with efficient operation structure for ME. The several additional components have been added to a comven-tional datapath base for ME acceleration. The results of its logic design...
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A large multi-port register file is an indispensable component to achieve higher computing performance, especially in recent processors. However, the number of its ports effects to circuit scale, access latency and power consumption significantly. Bank memory is one solution to implement a multi-port memory effectively. However, performance of the bank memory is lower than that of ideal multi-port...
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Single-ISA heterogeneous multi-core architecture which is composed of diverse cores, cache systems and shared bus system is promising technique to achieve higher energy efficiency. However, because heterogeneous multi-core processor (HMP) must be designed and verified each of cores, caches and shared bus system, an effort of implementing HMP is multiplied by the number of kinds of each of components...
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Reliable built-in self-test (Reliable BIST) scheme equips to be tolerant of faults, which occur in embedded BIST circuits. To realize reliable BIST, it is required to recover itself from transient errors of its embedded BIST circuits. In this paper, we propose a self-error-correctable response analyzer (RA) for a reliable BIST scheme. Experimental results show that test-reliability of SECRA is superior...
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Reliable built-in self-test (Reliable BIST) is a scheme in which embedded circuits used for self-testing circuits-under-test (CUTs) are designed to be tolerant of their faults. Reliable BIST is especially important for highly reliable on-line testing for real-time system, reliable BIST is required to recover itself from transient errors of its embedded BIST circuits. In this paper, we propose a transient...
