Integration, the VLSI Journal

article

Factored spherical subspace tracking

Filiep Vanpoucke, Marc Moonen

Integration, the VLSI Journal > 1995 > 20 > 1 > 3-19

Tracking the dominant subspace of a data matrix is an essential part of many signal processing algorithms. We present a modification to the so-called spherical subspace tracking algorithm. This algorithm has a low computational complexity, but suffers from accumulation of numerical errors. We show that this numerical instability can be circumvented by using a minimal orthogonal parameterization...

article

Algorithms and parallel VLSI architectures

M. Moonen, F. Catthoor

Integration, the VLSI Journal > 1995 > 20 > 1 > 1-2

article

A systolic algorithm for block-regularized RLS identification

J. Schier

Integration, the VLSI Journal > 1995 > 20 > 1 > 85-100

A modification of a systolic algorithm for recursive least-squares (RLS) estimation with inverse updates to implement block-regularized exponential forgetting is described. The regularization improves numerical stability of the algorithm, in comparison with the result obtained using exponential forgetting, if the input data is not sufficiently exciting (e.g. if the estimator is used as a part of...

article

The design of parallel square-root covariance Kalman filters using algorithm engineering

D.W. Brown, F.M.F. Gaston

Integration, the VLSI Journal > 1995 > 20 > 1 > 101-119

Megson and Comish (1994) have defined techniques using a systematic approach to derive a parallel algorithm for Riccati type equations. In this paper these techniques will be used to derive a full three-dimensional Hierarchical Signal Flow Graph (HSFG) for the square-root covariance Kalman filter (SRCKF) algorithm. This novel flow graph involves matrix-matrix multiplication, Givens rotations and...

article

Communication code generation in systems of affine recurrence equations

Christophe Reffay, Guy-René Perrin

Integration, the VLSI Journal > 1995 > 20 > 1 > 63-83

Following systolic array synthesis and parallelization techniques, this paper is devoted to code generation. A system of recurrence equations over an iteration space in Z ⁿ , a schedule and placement for the same being given, the method we propose here generates an equivalent distributed program. It handles the case where the schedule is a wavefront system, and the placement is a projection...

article

An algorithm and architecture based on orthonormal μ-rotations for computing the symmetric EVD

Jürgen Götze, Gerben J. Hekstra

Integration, the VLSI Journal > 1995 > 20 > 1 > 21-39

In this paper an algorithm and architecture for computing the eigenvalue decomposition (EVD) of a symmetric matrix is presented. The EVD is computed using a Jacobi-type method, where the angle of the rotations is approximated by an angle α _k , corresponding to an orthonormal μ-rotation. These orthonormal μ-rotations are based on the idea of CORDIC and share the property that performing the...

article

Scalable parallel processor array for Jacobi-type matrix computations

H.W. van Dijk, G.J. Hekstra, E.F. Deprettere

Integration, the VLSI Journal > 1995 > 20 > 1 > 41-61

This paper addresses the problem of designing a family of potential processor arrays for the execution of the so-called Jacobi algorithms. It extends the more familiar problem of designing a single fixed-size processor array for a particular program and it is parametrised with respect to size in two ways. Firstly, the program is no longer a particular one but is a member from a set of related programs...

article

An efficient lower bound algorithm for channel routing

Heng-Yi Chao, Mary P. Harper

Integration, the VLSI Journal > 1996 > 20 > 2 > 193-209

Channel routing plays a central role in the physical design of VLSI chips. For two-layer dogleg-free channel routing,d _m _a _x and v _m _a _x are the two traditional lower bounds. In this paper, we present two efficient algorithms for computing a tighter lower bound for the channel routing problem. Our algorithms successfully compute a lower bound of 26 for Deutsch's Difficult...

article

Resource-constrained scheduling of partitioned algorithms on processor arrays

Michéle Dion, Tanguy Risset, Yves Robert

Integration, the VLSI Journal > 1996 > 20 > 2 > 139-159

We deal with the problem of partitioning and mapping uniform loop nests onto physical processor arrays. Resource constraints are taken into account: not only do we assume a limited number of available processors, but we also assume that the communication capabilities of the physical processors are restricted (in particular, the number of communication links in each direction is bounded). This paper...

article

The Retiming Lemma: A simple proof and applications

Guy Even

Integration, the VLSI Journal > 1996 > 20 > 2 > 123-137

We present a new proof of the Retiming Lemma, which was first formulated and proved by Leiserson and Saxe (1981, 1983). Our proof relies on space-time transformations, and shows how retiming can be interpreted in the domain of space-time transformations. Two applications of the Retiming Lemma are given: one for designing circuits and the other for testing circuits.

article

A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation

P. Tzionas, A. Thanailakis, Ph. Tsalides

Integration, the VLSI Journal > 1996 > 20 > 2 > 211-237

A multi-valued pattern classifier with high discrimination sensitivity and its VLSI implementation proposal on a single chip are presented in this paper. The classification scheme is based on the combination of a reconfigurable Cellular Automaton and a Neural Network architecture. A 2-D Reconfigurable Hybrid Additive Cellular Automaton (RHACA) architecture amplifies the Hamming distance between...

article

A discrete formalization of switch-level circuit behavior

Wilbert H.F.J. Körver

Integration, the VLSI Journal > 1996 > 20 > 2 > 161-192

In [1], we developed a discrete switch-level circuit model for digital CMOS circuits. It describes the logic behavior -- static as well as dynamic -- of abstract transistor networks and captures logic faults due to conflicts, nondefined gates, hazards, charge sharing, imperfectness of switches, and relative timing problems. Although the model is directed towards CMOS, it is applicable to every FET...

article

Simultaneous area and delay minimum K-LUT mapping for K-exact networks

Shashidhar Thakur, F. Wong D.

Integration, the VLSI Journal > 1996 > 20 > 3 > 287-302

We address the technology mapping problem for lookup table FPGAs. The area minimization problem, for mappingK -bounded networks, consisting of nodes with at most K inputs, using K-input lookup tables, is known to be NP-complete for K 5. The complexity was unknown for K = 2, 3, and 4. The corresponding delay minimization problem (under the constant delay model) was solved in polynomial time by...

article

On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy

Amiya Nayak, Linda Pagli, Nicola Santoro

Integration, the VLSI Journal > 1996 > 20 > 3 > 327-342

Fault tolerance through the incorporation of redundancy and reconfiguration is quite common. The distribution of faults can have severe impact on the effectiveness of any reconfiguration scheme; in fact, patterns of faults occurring at strategic locations may render an entire system unusable regardless of its component redundancy and its reconfiguration capabilities. Testing of catastrophic faults...

article

Technology mapping for low power in logic synthesis

Vivek Tiwari, Pranav Ashar, Sharad Malik

Integration, the VLSI Journal > 1996 > 20 > 3 > 243-268

Traditionally, three metrics have been used to evaluate the quality of logic circuits - size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of this research, we have today very powerful techniques for synthesis targeting area and testability; and...

article

Fsm Test: Functional test generation for sequential circuits

G. Buonanno, F. Fummi, D. Sciuto, F. Lombardi

Integration, the VLSI Journal > 1996 > 20 > 3 > 303-325

This paper presents a new approach to test pattern generation for sequential circuits modeled as finite state machines. This approach is well suited for controller synthesis, because such devices are usually represented as explicit finite state machines. Based on a functional fault model, only a restricted set of transitions of the finite state machine (FSM) is considered for the purpose of testing...

article

An integral matrix-based technique for systematic systolic design

F. Lorenzelli, Yao K.

Integration, the VLSI Journal > 1996 > 20 > 3 > 269-285

In this paper we consider a systematic mapping procedure for systolic arrays. Integral matrix theory provides the basic concepts used here to define projection and scheduling vectors. Unimodular matrices are defined which describe projection, timing, and bases for the processor space and a correct timing function. The use of these matrices couples the definition of correct projection and scheduling...

article

Synthesis of systems specified as interacting VHDL processes

Petru Eles, Krzysztof Kuchcinski, Peng Zebo

Integration, the VLSI Journal > 1996 > 21 > 1-2 > 113-138

This paper presents an approach to synthesis of hardware systems specified as interacting VHDL processes. Different from traditional high-level synthesis methodologies our approach takes into account the interactions and interdependence between concurrent processes. Two methods have been developed. The first method supports an unrestricted use of signals and wait statements and synthesizes synchronous...

article

Performance optimization of VLSI interconnect layout

Jason Cong, He Lei, Koh Cheng-Kok, Patrick H. Madden

Integration, the VLSI Journal > 1996 > 21 > 1-2 > 1-94

This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees...

article

Built-in self-test for folded bit-line Mbit DRAMs

Emil Gizdarski

Integration, the VLSI Journal > 1996 > 21 > 1-2 > 95-112

In this paper an efficient and comprehensive algorithm for deriving near optimal parallel tests for neighborhood pattern sensitive faults (NPSFs) detection for an arbitrary type of neighborhood is presented. When k is odd (even) it is based on the decomposition of a directed (undirected) k-cube into a minimal number of edge-disjoint tours. The approach considerably simplifies test-pattern generator...

INFONA - science communication portal

Integration, the VLSI Journal

Factored spherical subspace tracking

Algorithms and parallel VLSI architectures

A systolic algorithm for block-regularized RLS identification

The design of parallel square-root covariance Kalman filters using algorithm engineering

Communication code generation in systems of affine recurrence equations

An algorithm and architecture based on orthonormal μ-rotations for computing the symmetric EVD

Scalable parallel processor array for Jacobi-type matrix computations

An efficient lower bound algorithm for channel routing

Resource-constrained scheduling of partitioned algorithms on processor arrays

The Retiming Lemma: A simple proof and applications

A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation

A discrete formalization of switch-level circuit behavior

Simultaneous area and delay minimum K-LUT mapping for K-exact networks

On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy

Technology mapping for low power in logic synthesis

Fsm Test: Functional test generation for sequential circuits

An integral matrix-based technique for systematic systolic design

Synthesis of systems specified as interacting VHDL processes

Performance optimization of VLSI interconnect layout

Built-in self-test for folded bit-line Mbit DRAMs

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