In the 21st century electronics, while we continue to approach the physical limits of MOSFET dimension scaling in the sub-10nm region, other new important drivers for digital computing and Internet of Things, have appeared on the research agenda. Among these, one is the energy efficiency of digital computing, from device to system level, which has direct impact on the power consumption (i.e. the energy consumed per computed bit of information). Minimizing power consumption is critical for modern electronics and is related to the voltage supply scaling, Vdd and standby Both dynamic power (proportional to Vdd2) power, (proportional to IoffVdd, and comparable or even dominant over the dynamic power in advanced technology nodes) depend on Vdd scaling. Until early 2000, the industry was able to scale Vdd according to Dennard's rule (happy scaling era) and from 2000 to 2010 this process was slow down but continued thanks to the introduction of new materials in CMOS engineering. However, after 2010 the voltage scaling is quasi-saturated at values close to 0.8V (Fig.1a). This is due to the fact that conventional electronics relies on thermal excitation of electrons over a barrier, necessitating an operating voltage many times larger than the thermal voltage, kBT/q, to maintain a good on-off ratio (>105) for a digital switch. This applies to any MOSFET switch and even to the so-called junctionless MOSFETs. Attempts to scale down further the threshold voltage, Vth, would generate an exponential increase in the off current, Ioff, of at least 10x for every 60mV of Vth reduction.