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In the 21st century electronics, while we continue to approach the physical limits of MOSFET dimension scaling in the sub-10nm region, other new important drivers for digital computing and Internet of Things, have appeared on the research agenda. Among these, one is the energy efficiency of digital computing, from device to system level, which has direct impact on the power consumption (i.e. the energy...
Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
An important component of the control with ion implantation of atomic penetration depth and dose is the precision control of the ion beam incidence angle on the material surface. For implant doping of planar CMOS junctions, angled implants of 30 to 45 degrees are used to place "halo" doping into the channel region under the gate and normal incidence (0 degree) implants are used to form symmetric...
Silicon semiconductor devices have remarkably been improved by the process scaling and introduction of some boosting technologies such as high-k/metal gate and strained silicon. However further improvement is quite difficult from the view point of mobility of silicon material. To overcome this problem, an increasing amount of attention has been devoted to the investigation of some higher carrier mobility...
In recent years Solid Source Doping (SSD) has been considered as a viable option in fabricating advanced CMOS devices [1], especially for forming shallow and highly doped junctions for source drain extensions (SDE) while minimizing the damage to the devices [2]. Current scaled devices require diffusion control in the nanometer range in order to form shallow SDEs using SSD. Additionally, high doping...
Low-temperature (≤200°C) formation of GeSn (substitutional Sn concentration: >8%) films on insulator is desired to realize high-speed thin film transistors (TFTs) and high-efficiency optical devices on flexible plastic substrates (softening temperature: ∼200°C). This is because GeSn (substitutional Sn concentration: >8%) has higher carrier mobility than Si and Ge due to the direct-transition...
Low temperature (≤500°C) formation of n-type crystalline Ge films on insulator is required to achieve the next-generation large-scale integrated circuits (LSI), where optical functions are merged. This is because n-type Ge shows high-efficiency optical functions owing to high electron population in the Γ band.
The recent FinFET scaling for 10–7nm node has resulted in significantly reduced contact areas for source/drain regions, leading to high contact resistance (Rc) [1-3]. Hence, it has become extremely critical to reduce the contact resistivity (ρc) to < 1×10−9Ω.cm2. ρc can be reduced by increasing the dopant concentration at the metal/semiconductor interface and by lowering the barrier height [4]...
The effect of traps in the hetero-junction and at the oxide interface on slope and ON-current of vertical and lateral InAs/Si Nanowire (NW) Tunnel FETs (TFETs) is demonstrated through physics-based TCAD analyses in combination with experimental findings. The high density of interface states (Dit) at the highly lattice-mismatched material interface degrades the sub-threshold swing (SS) and makes band-to-band...
Analysis of ultra-shallow junctions has become a critical requirement especially in the advent of new 3D device structures and technologies. Information derived from available traditional tools and concepts is no longer sufficient for use in TCAD tools for device performance optimization. Furthermore, the complex geometry and nanometer scale critical dimensions of current and future technology node...
In planar device technology, shallow junction is a structure to control source to drain off current leakage when the gate becomes narrow to keep up with scaling of semiconductor device. High spatial resolution characterization of the device junction position relative to the gate and its profile near the source and drain provide valuable input to device simulation and guidance of the complicated processes...
A great number of electronics devices are used in the information and communication equipment, and upgrading of the equipment largely depends on improving the performance of semiconductor devices, which are operated by controlling the migration of electron and hole within semiconductors. It is noted that the fine processing size for conventional semiconductor devices has been decreasing year by year...
This paper describes a basic concept relevant to deterministic transfer of molybdenum disulfide (MoS2) with optically transparent elastomeric stamp for constructing field-effect transistors (FETs). A simple fabrication process involving the formation of gate dielectrics and gate electrode, the deposition of source/drain contacts and the lamination of MoS2 flakes is established. The proposed method...
High-performance and low-power LSIs have been achieved by 3D transistor such as FinFET in logic and DRAM using crystalline-silicon channel and 3D-stacked devices in NAND flash using poly-crystalline-silicon channel [1]. For the future, monolithic transistors using atomic-layer materials are expected above the silicon devices [2]. A transition-metal di-chalcogenide (TMDC) such as molybdenum di-sulfide...
Germanium (Ge) is a promising candidate semiconductor for channel material of low power consumption and high performance field-effect transistors (FETs) alternative to silicon because of high hole and electron mobilities and good process affinity of Ge for the integration on Si nanoelectronics. One of serious issues of Ge for the practical FET application is a high parasitic resistance at metal/n-type...
Layered semiconductors of transition metal dichalcogenides (TMDC) have been considerable attention for both scientific interest and practical applications [1]. This paper describes a method to fabricate TMDC field-effect transistors (FETs) with heavily-doped silicon on insulator (SOI) substrate. The FETs are constructed by transfer of TMDC crystals on the surface of pre-patterned SOI substrate. This...
Three-dimensional (3D) ICs using TSVs are the most promising candidate for high performance and low power computing since they have lots of advantages such as short wiring length, small chip size, and small pin capacitances, as shown in Fig. 1 [1]. Until now, several kinds of 3D-ICs including image sensor chip, shared memory, and retinal prosthesis chip have been fabricated successfully.
As transistor technologies continue to scale and device density increases, junction formation requirements are subject to increasing challenges. Ion implantation is the preferred approach for junction formation due to its precise control of dopant depth and dose. These aspects are crucial to deliver finely tuned transistor performance and limit device variation. Arsenic and phosphorus (n-type) dopants...
In this paper the primary mechanisms for the plasma doping (PLAD) of 3D structures — direct implant, scattered implant, deposition & knock-in, and sputtering (etching) — are discussed. The TRI3DYN code was used to elucidate the roles these various doping mechanisms play. Through-fin SIMS profiles for an arsenic plasma doping process were calculated from the model and compared to experimental results...
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