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As transistor technologies continue to scale and device density increases, junction formation requirements are subject to increasing challenges. Ion implantation is the preferred approach for junction formation due to its precise control of dopant depth and dose. These aspects are crucial to deliver finely tuned transistor performance and limit device variation. Arsenic and phosphorus (n-type) dopants...
Three-dimensional (3D) ICs using TSVs are the most promising candidate for high performance and low power computing since they have lots of advantages such as short wiring length, small chip size, and small pin capacitances, as shown in Fig. 1 [1]. Until now, several kinds of 3D-ICs including image sensor chip, shared memory, and retinal prosthesis chip have been fabricated successfully.
The introduction of SiC Schottky barrier diodes has enabled further power loss reduction in high voltage power electronics, owing to its high operation speed [1]. Various electrode materials for diodes have been reported so far, including Mo, Ti and Ni [2]. However, interface reactions between these metals and SiC surfaces results in the formation of an inhomogeneous interface, which rises concerns...
Silicon semiconductor devices have remarkably been improved by the process scaling and introduction of some boosting technologies such as high-k/metal gate and strained silicon. However further improvement is quite difficult from the view point of mobility of silicon material. To overcome this problem, an increasing amount of attention has been devoted to the investigation of some higher carrier mobility...
In recent years Solid Source Doping (SSD) has been considered as a viable option in fabricating advanced CMOS devices [1], especially for forming shallow and highly doped junctions for source drain extensions (SDE) while minimizing the damage to the devices [2]. Current scaled devices require diffusion control in the nanometer range in order to form shallow SDEs using SSD. Additionally, high doping...
Pinning voltage (Vpin) is one of the most important parameters for the performance of CMOS image sensors and should be controlled in production. In this paper, we demonstrate Vpin control by direct measurement of the sheet resistance at micro test structures using micro point probe metrology before metallization. This method is quite useful for efficient development and quality control of CMOS image...
The increasing demand for higher performance of ULSI circuits requires aggressive shrinkage of device feature sizes in accordance with Moore's law. Plasma processing plays an important role in achieving fine patterns with anisotropic features in metal-oxide-semiconductor field-effect transistors (MOSFETs). Despite advancements in plasma processing, the degradation of material properties due to plasma...
Advanced inductively coupled plasma techniques and surface treatments have been used to demonstrate 5 nm conformal shallow junctions at low energy with no structure damage for both silicon (Si) and germanium (Ge). N-type PH3 plasma-assisted doping was characterized by dopant diffusion and electrical activation with increasing wafer temperature. Plasma-assisted doping at high wafer temperature showed...
Layered semiconductors of transition metal dichalcogenides (TMDC) have been considerable attention for both scientific interest and practical applications [1]. This paper describes a method to fabricate TMDC field-effect transistors (FETs) with heavily-doped silicon on insulator (SOI) substrate. The FETs are constructed by transfer of TMDC crystals on the surface of pre-patterned SOI substrate. This...
Germanium (Ge) is a promising candidate semiconductor for channel material of low power consumption and high performance field-effect transistors (FETs) alternative to silicon because of high hole and electron mobilities and good process affinity of Ge for the integration on Si nanoelectronics. One of serious issues of Ge for the practical FET application is a high parasitic resistance at metal/n-type...
In planar device technology, shallow junction is a structure to control source to drain off current leakage when the gate becomes narrow to keep up with scaling of semiconductor device. High spatial resolution characterization of the device junction position relative to the gate and its profile near the source and drain provide valuable input to device simulation and guidance of the complicated processes...
This paper describes a basic concept relevant to deterministic transfer of molybdenum disulfide (MoS2) with optically transparent elastomeric stamp for constructing field-effect transistors (FETs). A simple fabrication process involving the formation of gate dielectrics and gate electrode, the deposition of source/drain contacts and the lamination of MoS2 flakes is established. The proposed method...
The recent FinFET scaling for 10–7nm node has resulted in significantly reduced contact areas for source/drain regions, leading to high contact resistance (Rc) [1-3]. Hence, it has become extremely critical to reduce the contact resistivity (ρc) to < 1×10−9Ω.cm2. ρc can be reduced by increasing the dopant concentration at the metal/semiconductor interface and by lowering the barrier height [4]...
An important component of the control with ion implantation of atomic penetration depth and dose is the precision control of the ion beam incidence angle on the material surface. For implant doping of planar CMOS junctions, angled implants of 30 to 45 degrees are used to place "halo" doping into the channel region under the gate and normal incidence (0 degree) implants are used to form symmetric...
Germanium (Ge) is a potential candidates to replace silicon (Si) due to its higher carrier mobility, which is the key point for realizing device high-drive-current. However, fabricating highly activated np junction in Ge is challenging due to the severe damages introduced from ion-implantation interact with dopant during subsequent annealing process, and results in dopant deactivation. Further optimization...
Low Ohmic contact for p-type GaN (pGaN) has been of great importance for various applications including light emitting diodes and nitride based power devices. Although a low contact resistance (ρc) of the order of 10−6 Ωcm2 can be obtained with air-annealed Au/Ni electrodes, the hole transport relies on NiO islands inhomogeneously formed between the Au and the pGaN surface, giving concerns in long...
Magnesium silicide (MgSi) on Si use in Tunnel FET source-channel region that can improve the drive current to 2 order and more. In this work, we propose to deposit Mg and Si for multi-stacks by RF magnetron sputtering and evaluated the firmed Mg2Si. That has an atomically flat interface and surface are formed before and after annealing and Mg atoms encroachment into Si, therefore the Mg2Si on Si was...
We demonstrated the formation of ultra-shallow n+/p junctions in Si using an arsenic-doped Sol-Gel Coating (SGC) (Tokyo Ohka Kogyo Co., Ltd.) [1] and Flash Lamp Annealing (FLA). A high arsenic dopant concentration of 1.2×1020atoms/cm3 (Xj=9.0nm, Rs= 1203ohms/sq.) with a good junction profile (2.2nm/decade) was realized with 1.4ms FLA. These results indicate that this technique can be used for conformal...
Ion implantation and plasma etching are essential process steps for manufacturing semiconductor devices. The damage created by those process steps degrades device characteristics and reliability. Therefore, it is necessary to minimize the damage. The damage structure created by ion implantation is reconstructed during an annealing step, and p-n junction is formed as designed in advance. On the other...
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