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This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance gm, the output conductance gd, the intrinsic gain Av and the cut-off frequencies ft and fmax. Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly,...
We investigate the effect of interface states at the channel/insulator interface of III-V MOSFETs by means of accurate Schro¨dinger-Poisson and Multi-subband Monte Carlo simulations. Traps in the conduction band are found to be the main responsible of the Fermi level pinning observed in the experiments. These traps impact the mobility measurements as well as the current drive of short channel devices.
A simple analytic model based on the Kane-Sze formula is proposed to describe the current-voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model has fairly general validity and is not specific to a particular...
In this work, the conformal mapping technique is applied to obtain an analytical closed form solution of the 2D Poisson's equation for a double-gate Tunnel FET. The generated band profiles are accurate in all regions of device operation. Furthermore, the current levels are estimated by implementing the non-local band-to-band tunneling model from Synopsys Sentaurus TCAD. A good agreement with simulations...
Hall sensors play a pivotal rule among magnetic sensors. They are used for position sensing, speed control, current sensing and many other applications. Main limits in CMOS Hall sensors are sensitivity and acquisition bandwidth. While there is a strong literature on techniques able to increase sensitivity, bandwidth limits are not well understood. This paper analyzes the transient behavior of CMOS...
A study is presented on silicon oxynitride material for waveguides and germanium-silicon alloys for p-i-n diodes. The materials are manufactured at low, CMOS-backend compatible temperatures, targeting the integration of optical functions on top of CMOS chips. Low-temperature germanium-silicon deposition, crystallization and doping are studied for integrated photo-detection up to ∼1500 nm wavelength...
According to the ITRS the dimensions of the lower interconnect lines are expected to be reduced below 25nm for the years after 2014. In this work we investigate the properties of Cu nanolines in coplanar waveguide transmission line (CPW TLine) configuration for their potential use as RF interconnects in analog applications using the lower metal layers of the back-end-of-line (BEOL) CMOS processes...
In this paper we investigate the effect of current compliance during forming in HfO2-based Resistive Random Access Memories (RRAMs). We implemented a thorough statistical characterization of Random Telegraph Noise (RTN) in High Resistive State (HRS). Complex RTN signals are analyzed through a Factorial Hidden Markov Model (FHMM) approach, deriving the statistical properties of traps responsible for...
We present a framework for modeling the low-field mobility of ultra-narrow Si channels such as nanowires or FinFETs based on a full-band description of the electronic structure. Hole mobility is of particular interest since its calculation necessitates a full-band approach. Using cylindrical nanowires of different crystal orientation as a model for an ultra-narrow channel, we investigate the transport...
In this paper, we present an analysis of the degradation mechanisms in p-channel power U-MOSFETs due to Negative Bias Temperature Instability (NBTI). In particular, we study the influence of NBTI on threshold voltage and trans-conductance, which are the main figures of merit affected by charges trapping in the bulk oxide and by an interface defects generation. At the end of the stress, a recovery...
High-performance strained Silicon-On-Insulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with ION current of 1410 μA/μm (when IOFF = 70 nA/μm) at VDD=0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SSSAT = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an ION improvement up to +40%...
The hole mobility degradation due to remote dipole scattering in p-MOSFETs with TiN/HfO2/SiO2 gate stacks is studied based on the self-consistent solution of 6×6 k · p Schrödinger equation, multi-subband Boltzmann transport equations and Poisson equation using a deterministic (non Monte Carlo) solver. The dipole density assumed at the HfO2/SiO2 interface is consistent to the measured flat-band voltage...
SOI Si FinFETs scaled to gate lengths of 12.8 nm, 10.7 nm and 8.1 nm are simulated using 3D Finite Element Monte Carlo simulations with 2D Schro¨dinger based quantum corrections considering two cross-sections: rectangular and triangular, with rounded corners, in the preferred (110) channel orientation. The rectangular FinFETs give larger drive currents per perimeter than the triangular FinFETs but...
In the last few years the Tunnel-FET has become a promising device to be the successor of the classical MOSFET due to its steep switching behavior with subthreshold slopes (S) below 60 mV/dec. However, due to trap-assisted-tunneling (TAT) at the channel junctions the slope is significantly influenced. In this paper a 2D analytical band-to-band current model for ultra-thin body (UTB) single-gate (SG)...
In order to enable the simulation of statistical variability simulation in non-ideal device structures which arise from complex patterning steps, the GSS atomistic simulator, GARAND, has been enhanced for handling arbitrary 3D device geometries, and a structure translation tool MONOLITH has been developed to transfer the information about the device geometry, material composition and doping distribution...
Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are demonstrated. The voltage transfer characteristics as well as the inverter supply currents of both inverter types are analyzed and compared. A degradation of the inverter output voltage is observed due to the ambipolar TFET characteristics. Emulated TFET inverters based on the measured transfer characteristics...
A novel device technology for photonics integrated circuits (PICs) is presented. In this work germanium PIN photodetectors are embedded in back-end deposited high-k slot waveguides. The waveguides are fabricated using chemical vapor deposited amorphous silicon and atomic layer deposition of Al2O3 thin films. The germanium PIN stack is selectively grown on a bulk silicon substrate. The detectors are...
We report on a wafer scale fabrication of graphene based field effect transistors (GFETs) for use in future radio frequency (RF) and sensor applications. The process is also almost entirely CMOS compatible and uses a scalable graphene transfer method that can be incorporated in standard CMOS back end of the line (BEOL) process flows. Such a process can be used to integrate high speed GFET devices...
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