The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper we present fully-integrated field probes for real-time trajectory mapping during magnetic resonance imaging (MRI) experiments. The field probes co-integrate an NMR microcoil and the required transceiver electronics on a single ASIC manufactured in a 0.13µm CMOS technology. Thanks to an on-chip PLL, power amplifier and low-IF quadrature receiver, all connections to and from the chip carry...
For 1.0V operation NAND flash memory, heterogeneously integrated voltage generator is proposed and experimentally demonstrated. The proposed 2-stage boost converter uses high voltage (HV) transistors of standard CMOS process as the 1st stage and HV transistors of NAND flash process as the 2nd stage. The intermediate load capacitance is adaptively adjusted according to the number of NAND flash chips...
We have developed a physics based model for negative capacitance (NC) FinFETs by coupling the Landau-Khalatnikov model of ferroelctric materials with the standard BSIM-CMG model of FinFET. We apply our model to thin film Y-HfO2 (yttrium-doped hafnium oxide) based NC-FinFETs designed using state of the art 22nm technology node FinFETs. Using the same ferroelectric material, we demonstrate a device...
A 32-bit icyflex2 processor operating over a wide supply range (WSR) is presented, showing a very low energy consumption in comparison to other state-of-art 32-bit processors. Operating under very different supply conditions involves tremendous differences in operating frequency, and a large sensitivity to process and temperature variations at low-voltage, which both tend to complicate timing closure...
An inductive coupling technique for wireless interconnection of side-by-side chips within a package is presented. Data is transferred by using changes in magnetic field that occur when the current in coils on the chips is switched off. The circuit layout area and power consumption of transceivers have respectively been reduced to 1/3 and 1/6. A world-leading transmission rate of 1 Tb/s/mm2, which...
The floating-point unit is one of the most common building block in any computing system and is used for a huge number of applications. By combining two state-of-the-art techniques of imprecise hardware, namely Gate-Level Pruning and Inexact Speculative Adder, and by introducing a novel Inexact Speculative Multiplier architecture, three different approximate FPUs and one reference IEEE-754 compliant...
A digitally controlled 2-/3-phase 6-ratio switched-capacitor (SC) DC-DC converter with low output voltage ripple and high efficiency is presented. Operating with a wide input voltage range of 1.6V to 3.3V, this SC converter can deliver a maximum power of 250mW to an output of 0.5V to 3V. Six voltage conversion ratios (VCRs) can be generated with only 2 flying capacitors by using 2- or 3-phase operation...
On-chip supply boosting can quickly restore a microprocessor core's power rail from near-threshold to super-threshold when critical code sections are encountered. We demonstrate a flip-chip implementation of a supply boosting technique, called Shortstop, which uses a transient supply rail and leverages the parasitic and intentional inductance of a package. To address package parasitic variation, an...
A fully-digital, single-loop Unified Voltage and Frequency Regulator (UVFR) is designed in 130nm CMOS to provide the correct supply to digital loads to meet a timing criteria. Simultaneously a Tunable Replica Circuit (TRC) based local oscillator is generated from the regulated supply and clocks the load. Measurements show 0.84V to 0.27V range of operation, and 27% supply guardband reduction at iso-performance...
In various fields, there is a growing need for electric motor drives and inductive power converters. To achieve better switching behavior and lower EME in inductive switching applications, very precise gate control of the power MOSFETs by the gate driver is required. The driver presented in this paper can operate at voltages up to 60V, and it is able to change the gate current in 10 / 15ns (rise /...
A sub-ps ΔΣ TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and ΔΣ TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm2.
A hybrid (digital and analog) low dropout regulator (LDO) utilizing switched mode control is designed in 130 nm CMOS for fine grain power management, fast droop recovery and robust small signal regulation of multi-VCC digital loads. The design provides an optimal trade-off of performance and accuracy by switching between a digital and an analog control loop. The hybrid topology achieves robust small...
A receiver for efficient wireless power delivery at 6.78MHz from smartphones to IoT devices has been designed in 0.18 µm CMOS. The receiver implements a technique to estimate the end-to-end efficiency and achieve maximum efficiency-point tracking (MEPT) across the charge cycle of a Li-ion battery without needing an explicit communication channel with the transmitter. The MEPT technique is tested using...
A stability-improved single operational amplifier third-order ΣΔ modulator by using a fully-passive noise shaping SAR ADC as a quantizer is presented in this paper. One operational amplifier is shared to realize 2nd order noise shaping and an additional 1st order noise shaping is realized by a fully-passive technique in the quantizer. An additional switch and capacitor path is introduced to the operational...
This paper presents a high dynamic range (DR), power efficient VCO-based continuous time ΔΣ modulator (CTDSM). It introduces a simple, robust and low power fully digital phase extended quantizer (PEQ) that doubles the VCO quantizer resolution compared to conventional XOR-based phase detector with minimum overhead. A tri-level resistor DAC is also introduced as complementary to the new quantizer, enabling...
We propose wear-out estimator of remaining lifetime, which consists of two types of custom ring oscillators (ROs) and cumulative stress counters only. This on-chip estimator operates independently without disruption of MCU main operations and is aimed for advanced automotive MCUs, which demand sufficient reliability and real-time response along with high performance in cutting-edge applications such...
This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments...
This work presents a RISC-V system-on-chip (SoC) with integrated voltage regulation and power management implemented in 28nm FD-SOI. A fully integrated switched-capacitor DC-DC converter, coupled with an adaptive clocking system, achieves 82–89% system conversion efficiency across a wide operating range, yielding a total system efficiency of 41.8 double-precision GFLOPS/W. Measurement circuits can...
A prototype neuromuscular interface with distributed sensing and stimulation functions was developed to evaluate power isolation and maximize stimulation artifact rejection. Evaluation was performed in saline with representative stimulating and sensing electrodes. Stimulation pulses paced at 100 Hz were applied while sensing frequencies from 2.5 to 500 Hz. Two isolation topologies were evaluated,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.