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We apply the bimodal trap model of Random Telegraph Noise (RTN) to predict its impact on the circuit level instead of the conventional unimodal trap model. Two different trap distributions represented by the average number of traps N and the average impact to threshold voltage Vth per trap η in gate dielectric make measured RTN distributions of ring oscillators (ROs) to follow the bimodal trap model...
The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three key device aspects — stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond...
We present hot-carrier degradation analysis for SiGe heterojunction bipolar transistors based on deterministic solutions of the Boltzmann transport equations for a coupled system of electrons and holes. The full-band transport model provides the distribution function of the charge carriers interacting with the passivated Si-H bonds along the Si/SiO2 interface. Investigation of the density of hot carriers...
As the dimensions of electronic devices, especially transistors, are getting smaller and smaller, novel modeling approaches must be developed to reveal the physics and predict the performance of not-yet-fabricated ultra-scaled components. In this paper the basic requirements to simulate nanoscale devices are first reviewed before introducing a hierarchical quantum transport approach going from empirical...
Soft-errors are one of the most important reliability issues in logic and memory circuits. Proper estimation of soft-error-rate (SER) is important for error mitigation and SER robust circuit design. This paper presents a physical charge collection model for accurate simulation/prediction of SER in FinFETs. The modeling is scalable and includes the effect of variation of FinFET process and layout parameters.
Spin-charge correlated dynamics is currently of great interest, because it allows to control the electric current and to obtain the large experimentally observed magnetic field dependent responses suitable for various practical applications. Resonant trap-assisted tunneling in heterostructures with ferromagnetic contacts explains the signal magnitude in three-terminal spin-injection experiments by...
We investigate the anisotropic behavior of dry and wet thermal oxidation of silicon carbide for which a high-accuracy three-dimensional simulation model is entirely missing. To bridge this gap, we propose a direction dependent interpolation method for computing oxidation growth rates for three-dimensional problems. We use our method together with available one-dimensional oxidation models to simulate...
Conventional CMOS scaling and the Moore's law have been the cornerstone of progress in computing hardware technology. However, with dimensional scaling expected to end soon, there is a pressing need to find the next transistor solution that can continue to support the technology revolution. Will this hardware solution be an enhanced or an augmented version of MOSFET or a switch based on a radically...
In this work, we concentrate on extending our optimization method for IGBTs [1] in drives applications by incorporating diode parameters in addition to IGBT parameters. For this purpose, the fabrication process of the diode, including a platinum diffusion and it's parameters for lifetime adjustment [2], was added to the optimization loop. Consequently, the simulation of an IGBT turn-on event in the...
A deterministic Boltzmann equation solver for graphene sheets is developed. The self-heating effect is included. The Boltzmann transport equation is expanded with the Fourier harmonics. The remote phonon scattering as well as the intrinsic phonon scatterings are considered. The angle-dependent term of the remote phonon scattering is accurately implemented. Impact of the maximum order of the Fourier...
Current filaments are inherently three-dimensional phenomena regardless of the chip topography, which can be stripe-or checkerboard-shaped. Therefore, we consider an alter-native mapping of the real-chip IGBT cell topography to a quasi-3D simulation geometry in order to attain a computationally affordable approximation of 3D-filamentation effects that limit the SOA. The new approach extends that of...
A compact model of IGBT (Insulated-Gate Bipolar Transistor) is developed by considering the high-injection condition explicitly. The model distinguishes the MOSFET controlled part and the bipolar transistor controlled part explicitly by introducing internal potential nodes, which are solved iteratively. It is verified that the model calculates the potential distribution along the device identical...
We present for the first time an equipment simulation study for a reactor for plasma-enhanced oxidation powered by 10 individually tunable microwave sticks. The simulated dependence of the oxidation rate on the distance between the sticks and the wafer and the simulated across wafer-uniformity well agree with measured data. The presented methodology allows one to study and optimize the process with...
In this paper, we propose a surface-potential-based simulation model of SiC power MOSFETs for accurate circuit simulation. By considering physical structure and behavior of vertical power SiC MOSFETs, the proposed model reproduces static and dynamic characteristics upon wide range of bias voltages. Through experiments using a commercial SiC power MOSFET, good agreements have been observed between...
As logic devices continue to downscale, interconnections are reaching the nanoscale where quantum effects are important. In this work we introduce a semi-empirical method to describe the resistance of copper interconnections of the sizes predicted by ITRS roadmap. The resistance calculated by our method was benchmarked against DFT for single grain boundaries. We describe a computationally efficient...
We present a comprehensive simulation framework for transport modeling in nano-scaled devices based on the solution of the subband Boltzmann transport equation (BTE). The BTE is solved in phase space using a k·p-based electronic structure model and includes all relevant scattering processes. The BTE solver is combined with a conventional drift-diffusion-based simulator using a novel iteration approach...
A novel normally-off AlGaN/GaN HFET (Rake-Gate HFET), based on stress and layout engineering without modifying typical fabrication processes is proposed. It is verified and optimized through TCAD simulation. Positive pinch off voltage is achieved by depositing compressively stressed passivation nitride surrounding gate tines, which induce significant negative piezoelectric charge under the tines....
Process simulations provide vital insights to identify the key process steps to dedicate wafer resources for improvement or to determine investment on tool capability. We considered this problem in the context of an industry-like 5nm Back-End-of-Line flow being developed in IMEC and modeled the approximately 150 step process flow in COVENTOR SEMulator3D®. For the first time a one-million wafer Design...
With the growing interest in III-V-based nano-scale transistors as potential candidates for next-generation switches there is a need for efficient simulation tools capable to predict the impact of inherent quantum effects. In this paper we show how quantum drift-diffusion (QDD) models can be used to mimic those quantum effects. The models do not only properly account for geometrical confinement in...
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