The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Dimensional scaling will continue in Si CMOS technology which will extend to beyond 10nm. Key challenges for dimensional scaling and expansion of silicon-based technologies as well as research directions will be reviewed in traditional semiconductor applications such as DRAM, NAND Flash, logic as well as advanced devices including STT-MRAM, ReRAM and reconfigurable logic. Furthermore, other areas...
The 42th European Solid-State Device research conference (ESSDERC 2012) runs in parallel to his sister conference ESSCIRC 2012, covering all aspects of modern solid-state systems, circuits and devices at a single event. This year, a total of 130 submissions originating from 28 countries were received for ESSDERC including 83 papers coming from Europe, 37 from Asia-Pacific and 10 from North-America...
The R&D maturity level reached by the Silicon Photonics technology envisions a clear road map fitting the needs and the challenges of the future ICT (Information Communication Technology) systems and services. Four key applications will drive the evolution: intensive computing, broadband communication, mass storage and consumer multimedia. The Silicon Photonics technology, ported in the 300 mm...
Solid-state electronic devices can be engineered to detect and manipulate biological molecules and cells by using electric or magnetic interactions. The integrated circuits, which can contain a large number of such devices, may then potentially be developed into low-cost chip-scale platforms to perform bioanalytical tasks in a multiplexed manner for applications in biology, biotechnology, and personalized...
This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic...
Benchmarking figures for graphene show remarkable properties like ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs [1, 2]. When graphene is integrated and processed, however, defects in the graphene and its dielectric environment dominate device performance [3, 4]. Furthermore, the lack of a band gap limits the applicability of graphene field...
After six decades of device size reduction and its efficient use through hierarchical design, the semiconductor area encounters two major conflicting currents: (a) quantum, stochastic (atomic and signal/noise) and other probabilistic effects with size reduction at the bottom and (b) thermodynamic consequences in the inefficiencies of the information engine as a large numbers of devices are assembled...
This talk will summarize our work in the last three years exploring the possibility of spin-magnet circuits that utilize two key recent advances, namely (1) spin valve (SV) devices demonstrating spin injection into metals and semiconductors from magnetic contacts and (2) spin transfer torque (STT) devices demonstrating the switching of magnets by the injected spins. Utilizing an experimentally benchmarked...
Organic thin-film transistors (TFTs) can usually be fabricated at temperatures of about 100 °C or less and thus on a variety of unconventional substrates, such as flexible plastics and paper. This makes organic TFTs potentially useful for the integration with organic light-emitting diodes (OLEDs) into bendable, rollable or foldable emissive active-matrix displays for next-generation mobile devices,...
BSIM compact models have served industry for more than a decade starting with BSIM3 and later BSIM4 and BSIMSOI. Here we will briefly discuss the ongoing work on current and future device models in BSIM group. BSIM6 is the next generation bulk RF MOSFET Model which uses charge based core with physical models adapted from BSIM4. Model fulfills all symmetry tests and shows correct slopes for harmonics...
The aggressive downscaling of advanced bulk CMOS technologies demands MOSFET models that are able to describe accurately the behavior of devices accounting for all the physical phenomena. A reliable model should have the ability to handle all the different operating regions of the MOS transistor in the whole geometry range of one technology. Targeting to meet the aforementioned needs, the new charge-based...
This paper reports on the extraction of the small-signal equivalent circuit of 28nm isolated RF MOS transistors using on-wafer 4-port S-parameter measurements up to 50GHz. It shows that modeling accuracy of RF MOS is significantly enhanced via a 4-resistance cross-type substrate network plus an isolation sub-network. In addition, the impact of substrate network on Mason gain is presented. Finally,...
Standard cell libraries are designed focusing on the best performance-area trade-off for a technology at nominal supply. Scaling supply voltages emphasizes the effects of systematic or random variation. We revisit existing approaches and present two new design points in standard CMOS that target variability hardened standard cells integrated into the digital design flow. They are optimized for dynamic...
This paper presents a new physics-based method for reliability prediction and modeling of Integrated Circuits (ICs). By implementing transistor degradation mechanisms via differential equations in the transistor compact model, the aging of the circuit can be simulated over (accelerated) time under real conditions. Actually, each transistor in the circuit integrates the voltage, current and temperature...
This paper presents an overview of the design challenges and solutions under development for Nano-scale technologies. Major applications requirements and nano-technologies design limitations are introduced. Adaptive techniques aiming to cope with variations and to track an optimal energy operating point are presented.
We report an experimental study of the carrier transport in long channel tri-gate (TG) and omega-gate (ΩG) Si nanowire (NW) transistors with cross-section width down to 10 nm. Electron and hole mobility have been measured down to 20 K. We discuss the influence of channel shape, channel width and strain on carrier mobility. In particular we have shown that transport properties are mainly driven by...
InGaAs-OI and GeOI SRAM cells using optimized threshold voltage (Vt) design to enhance the intrinsic variation immunity of high-performance (super-threshold) and low-voltage (near-/sub-threshold) 6T SRAM cells are presented. For low-voltage SRAMs operating at low Vdd, low-Vt design shows smaller variability while the design trade-off between performance and leakage should be considered. For highperformance...
We fabricated ultrathin HfO2 gate stacks of very high permittivity by atomic layer deposition (ALD) and novel two-step post-deposition annealing (PDA) technique. First, no-cap PDA degasses residual contaminations in ALD layer, and second, Ti-cap PDA enhances permittivity of HfO2 by generating cubic crystal phase without SiO2 interfacial layer growth. Using these techniques, the dielectric constant...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.