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Micro and nano systems (MNS) and Nano scaled devices, that are capable of handling fluids and to interact with DNA and proteins enable bio analysis at the “ultimate” molecular level and are prone to be coupled to IC Technology. This paper includes recent developments in that area that aim to illustrate the diversity and potential of the MNS approach: (1) Micromachined tweezers with sharp tips successfully...
This paper presents a continuous, physically and charge-based new model for triple gate junctionless nanowire transistors (3G JNT). The presented model was evolved from a previous one designed for double gate junctionless transistors (2G JNT). The capacitance coupling and the internal potential changing from 2G to 3G JNTs are considered. The model validation is performed through both numerical simulation...
For the first time, we report the operation of Single Electron Transistors (SETs) and Single Hole transistors (SHTs) up to 350K from Q-gate CMOS transistors at ultimate scaling. These results are obtained with gate lengths (LG) scaled down to 10nm and ∼3.4nm diameter silicon nanowires (Si-NWs). The SETs and SHTs exhibit Coulomb oscillations in the nanoampere range up to 350 K which can be amplified...
The impact of nanowire (NW) height and Si0.7Ge0.3:B source-drain (S/D) on the performance of p-type trigate NW is presented. We show that an increase in Si NW height from 14.5nm to 24nm generates up to +30% enhancement in hole effective mobility for a 13nm NW width. Effectiveness of Sio.7Geo.3:B S/D is then discussed for a wide range of NW width (13nm<W<218nm) and height (11nm<HNw<24nm)...
Reconfigurable silicon nanowire field effect transistors (RFETs) provide both operation modes of p-type and n-type field effect transistors in a single multigate device. This unique feature provides additional degrees of freedom in terms of circuit design and device layout. Here a device-circuit co-design study of a novel 1-bit full adder with only 20 transistors is presented. The delay of the adder...
We present two schemes for carrier transport treatment to be used with our hot-carrier degradation (HCD) model. The first version relies on an exact solution of the Boltzmann transport equation (BTE) by means of the spherical harmonics expansion (SHE) method, whereas the second one uses a simplified drift-diffusion (DD) scheme to avoid the computationally expensive SHE approach. We use both versions...
A TCAD-based approach has been used to investigate the leakage current and breakdown regime of vertical GaN/AlGaN/Si structures at different ambient temperatures. A good agreement with experimental data has been obtained by implementing both trap-assisted and Poole-Frenkel conduction mechanisms into the buffer layers. The latter mechanisms have been proven to anticipate the onset of breakdown at high...
The purpose of this study is to evaluate the ESD protection behavior using BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. Using as a reference our measurements in hybrid bulk structures we extend the BIMOS design towards the ultrathin silicon film. Evaluations are done based on 3D TCAD simulation with standard physical models using ACS method...
A new latch-free LIGBT on SOI is presented. The new device combines advantages from both LDMOS as well as LIGBT technologies; high breakdown voltage, high drive current density, low control voltages, at the same time eliminating latch-up problems. Breakdown voltage of over 200 V, on-state current density over 3 A/mm and latch-free operation is demonstrated.
This paper presents the main recent achievements of the UTBB-FDSOI technology. It shows some of the power advantages of the 28nm technology node today used for production. It details the 14nm nodemain features with the first generation of boosters. It finally indicates some technology bricks under development for the 10 nm generation.
In this work self-heating and its effect on device parameters are compared in 28 nm technology bulk and FDSOI MOS devices. It is found that the thermal resistance is ∼3.4 times higher and the temperature rise is ∼2.5 times higher in FDSOI than in bulk However, in spite of stronger self-heating, FDSOI devices outperform bulk over a wide frequency range. Moreover, device parameters degradation with...
As device dimensions are scaled down, the use of non-geometrical performance boosters becomes of special relevance. In this sense, strained channels are proposed for the 14 nm FDSOI node. However this option may introduce a new source of variability since strain distribution inside the channel is not uniform at such scales. In this work, a MSB-EMC study of different strain configurations including...
We have studied the mobility in the FDSOI devices as a function of silicon thickness, doping, surface orientation and applying different back biases. This study is also done in the near-spacer-region that is partially inverted. Simulations have been obtained with a self-consistent Poisson-Schrödinger which provides a precise energy distribution of carriers and, allied to a Kubo-Greenwood carrier mobility...
We report an extensive experimental study of CMOS-compatible switches based on vanadium dioxide abrupt metal-insulator transition. We perform scaling studies to provide guidelines for optimization of the geometry of the VO2 device for integration on CMOS circuits, discussing the trade-off between the design parameters and the effect on performance for DC and RF applications. A VO2 thin film with resistivity...
In this work we investigate the effects of different interface trap density distributions (Dit) on the electrical and power performances of a Gate-All-Around In0.53Ga0.47As/In0.52Al0.48As Nanowire Superlattice-FETs (GAA NW SL-FET) using Al2O3 and HfO2/La2O3 as gate dielectrics. This analysis shows that a high At content at the high-K/InGaAs interface causes degradation of the subthreshold characteristics...
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