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The European Logarithmic Microprocessor (ELM) had been an outstanding breakthrough in logarithmic number system (LNS) research history. The processor successfully reaches the par ability of floating-point (FLP) processor with its rapid and accurate design towards FLP. The design was able to improve the LNS addition and subtraction procedure, which are the drawbacks of any implementation of LNS arithmetic...
Interpolation is among of the most popular approach used in approximating the values in logarithmic number system (LNS) arithmetic design. This method that often combines with lookup tables (LUTs) manages to produce efficient LNS design in area, latency and accuracy. Current research proves that the combination of interpolators with co-transformation in LNS subtraction had shown extreme improvements...
This paper presents a harmonic elimination pulse width modulation (HEPWM) of five-level cascaded inverters using particle swarm optimization (PSO). The goal of this switching technique is to eliminate the lower order harmonic and satisfied the fundamental component at the same time. To solve the non-linear transcendental equation for the different modulation index of a five-level inverter with 7/9...
A 160 MHz gm-C low-pass filter designed based on a lossy integrator synthesis is presented in this paper. The lossy integrator synthesis is used which takes into account losses due to finite DC gain of the transconductor in the integrator. The method used is thoroughly shown in this paper. The designed system level 160 MHz gm-C filter is simulated and the result shows an undistorted frequency response...
Logarithmic number system or LNS has become an optimal choice in digital image processing instead of floating point (FP) system based on latest researches in LNS. Digital image processing which deals with a lot of complex operations such as multiplication and division, makes LNS as a great choice of implementation. However, the implementation had been restricted by the addition and subtraction function...
A high linearity CMOS up‐conversion mixer at 3.0–5.0 GHz for ultrawideband applications is presented. The proposed design is implemented in TSMC 0.18‐μm CMOS technology. A Gilbert‐cell active double‐balanced mixer using a capacitor placed in parallel with the intrinsic gate‐source capacitor of a core mixer to improve linearity is used. To further improve the linearity and input matching, source degeneration...
Logarithmic number system (LNS) has been a trend in digital signal processing (DSP) for recent years, particularly digital image processing. LNS was been implemented in DSP processors and even as an enhancer tool in image improvements. The selection of LNS is due to the ease of operation for multiplication, division, square and square-root which been replaced by fixed-point addition, subtraction,...
A current-steering Digital to Analog Converter (IDAC) to compensate dc-offset of a baseband chain in a Synthetic Aperture Radar (SAR) receiver is presented in this paper. The differential dc-offset can be injected with the current steer controlled by 9 digital control bits. The simulated LSB is 1.4 mV and the differential voltage range is 283 mV when it is connected to the baseband chain. This IDAC...
This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers,...
The best security factor in any encryption algorithm is the random values used in key management or the structure of the algorithm itself. Thus, some of the encryption algorithm employed random number generator to produce this type of numbers. This paper describes the process of selecting the most efficient algorithm to represent the hardware RNG for the usage in cryptography. For this purpose, a...
Thispaper discusses the design of an operational transconductance amplifier (OTA) circuit foruse in a capacitive sensor interface circuit. The OTA converts a differential voltage input into the current as part of a switched capacitor integrator module. In this paper, a two-stage OTA is proposed which has high gain, high output swing and low noise. The circuit wasimplemented using 0.13μm Silterra CMOS...
High power LED are captivating attention due to its cogent impacts on lighting industry in terms of efficacy, low power consumption, long lifetime and miniature physical size. Nonetheless, the efficiency and reliability of the LED is signified by the junction temperature. This work demonstrates the thermal and stress simulation of single chip LED package with 1mm x1mm x 1mm copper heat slug. The simulation...
The reliability of the solder joints of Ball Grid Array is severely tested during the exposure of thermal operation due to coefficient of thermal expansion (CTE). Different thermal expansion due to this mismatch causes shearing effects to the solder joints. This paper compares the shearing speed on stress and strain between Sn-3.9Ag-0.6Cu and Sn-3.5Ag-0.7Cu solder ball. A full factorial design of...
Interconnection technology has improved by leaps and bounds since the advent of solder reflow. This has made surface mount technology more robust. Ball Grid Array (BGA) is a demanding surface mount chip package in Integrated Circuits (IC) which uses a grid of solder balls as its connectors. In this preliminary study, load effects of shear test on a single solder joint with varied parameters are briefly...
A revolution to illumination industry, the high power light emitting diodes, LEDs have significant dominance in terms of optical performance, low power consumption and superior reliability over conventional lights. In spite of that the junction temperature of the LED is an imperative aspect which manipulates the consistency of the LED. This study discusses the thermal and stress analysis of single...
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