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FPGA-based neural-networks typically leave performance on the table because the DSP resources run at less than a third of the peak clock rate. This paper presents a processing array architected to consistently achieve timing closure at 100% of the peak DSP clock rate with standard FPGA tools. In the HDL design environment, our processing array operates at the peak DSP clock rates on Xilinx UltraScale...
This paper reviews the interconnect and package design of a heterogeneous stacked-silicon FPGA. Up to five dice from two die types are mounted on a passive silicon interposer. A hardware- and software-scalable FPGA family can be created by mixing different combinations of these two die types. The FPGA, inside a low-temperature co-fired ceramic (LTCC) package, consists of two silicon die types-up to...
This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic...
This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic...
This article consists of a collection of slides from the author's conference presentation on Xilinx's field programmable gate arrays (FPGA) that deploy 28 Gb/s transceivers built with heterogeneous stacked silicon interconnects. Some of the specific topics discussed include: key applications for use; the special features and specifications of the FOGA family of Xilinx products; stacked-silicon packaging;...
This article consists of a collection of slides from the author's conference presentation on the deployment of optical backplanes with 3D integrated photonics. Some of the specific topics discussed include: a performance analysis between electrical versus optical backplanes; a comparison betwen optical systems versus optical backplane technology; and the effective deploymet of chip stacking.
As line interfaces in communications chassis transition to 100 Gb/s and higher per port, many in the industry question when electrical backplanes inside these chassis will give way to optical ones. Provided that the maximum card-to-card distance over a backplane remains at one meter, two observations point to an electrical-to-optical transition near the end of this decade: commercial links transition...
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