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A 56Gbps PAM-4 optical receiver front-end is presented. In order to reduce the input-referred current noise of the receiver front-end, the shunt feedback resistor Rf of the TIA is enlarged. And, the equalizer is inserted to boost the high-frequency gain and extend the bandwidth. The AGC amplifier using the proposed dB-linear VGAs is further to lower the noise. This PAM-4 optical receiver front-end...
A 2×25 Gb/s clock and data recovery circuit is fabricated in a 40-nm CMOS process. A background amplitude-locked loop is proposed to reduce the amplitude variation of a charge-steering-logic return-to-zero latch. The measured rms jitter is 2.26 ps and the peak-to-peak jitter is 15.56 ps for a 25 Gb/s PRBS of 27-1. It dissipates 8.8 mw per channel from 1.15 V supply.
A 3–25 Gb/s four-channel receiver with noise-canceling transimpedance amplifiers and power-scalable limiting amplifiers is presented. It is fabricated in a 40-nm CMOS process. Each channel provides an overall gain of 64 $\hbox{dB}\cdot \Omega$. The measured input integrated noise is 2.7 $\mu\hbox{A}_{\rm rms}$, and the measured bit error rate is $< 10^{-12}$ for a 25-Gb/s pseudorandom bit sequence...
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