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Timing prediction has become more and more difficult with shrinking technology nodes. Combining the pre-silicon delay model with post-silicon timing measurements has the potential to improve the accuracy of timing analysis. In this work, we address the problem of automatic test pattern generation for understanding circuit timing sensitivity to power supply noise (PSN) during post-silicon validation...
In this work, we address the problem of automatic test pattern generation for understanding circuit timing sensitivity to power supply noise (PSN) during post-silicon validation. Pseudo functional test patterns targeting the longest paths captured by each flip-flop are first generated. To determine the sensitivity to on-chip noise, the patterns are intelligently filled to achieve the desired PSN level...
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