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Proper generation of power law (1/fα) noise for the simulation of atomic clocks has been a topic of research for a long time. Yet one important class of algorithms, namely fractional Brownian motion, has seen very little attention in the time and frequency control community. We aim here to review the current state of research in fractional Brownian motion, how it can be applied to atomic clocks and...
Time interval counters based on the excitation of harmonic filters offer the promise of achieving sub-picosecond precision with seemingly simple systems. Unfortunately, the components used in such a system have very stringent requirements, making them both complex and expensive to build. We have investigated ways to relax the requirements on the components, simplify the circuitry, and the effects...
Clock ensembles are at the core of many applications in which precise time or frequency is required. The widely used time scale algorithms need cumbersome modifications when clocks can be potentially faulty. Fault-tolerant clock synchronization algorithms from distributed systems allow to build time scales without the need of special detection systems for anomalous behavior of the clocks. We present...
Using software defined radio (SDR) systems for time and frequency metrology offers the possibility to perform measurements with high precision. Common off the shelf SDR systems are not always a good match for metrological applications as they do not generally offer ways to lock the local sampling clock to an external source or have lax noise requirements. We have built a flexible platform for SDR...
Multiplexers (MUXes) are ubiquitous in digital circuits. A MUX processes inputs a, b and a select bit s to output a if s = 0 and b otherwise. Hence, in the case of a = b, the output must be a, regardless of s. Unfortunately, common MUX implementations violate that specification if s is degraded. We propose efficient transistor-level implementations of Metastability-Containing Multiplexers (CMUXes)...
We propose a novel method for transforming delay-line time-to-digital converters (TDCs) into TDCs that output Gray code without relying on synchronizers. We formally prove that the inevitable metastable memory upsets (Marino, TC'81) do not induce an additional time resolution error. Our modified design provides suitable inputs to the recent metastability-containing sorting networks by Lenzen and Medina...
We present the first FPGA implementation of a distributed clock synchronization algorithm with sub-nanosecond skews that can tolerate arbitrary faults of individual components. Each of n nodes is equipped with its own quartz oscillator and the nodes broadcast their clock pulses to enable synchronization. The algorithm provably maintains synchronization even if fewer than n/3 nodes exhibit arbitrary...
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