The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f2 phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence...
This paper presents a new way of modeling the integrators non-idealities for high-level sigma-delta modulator models. In this way, designers can correlate directly the integrator specifications like finite DC gain, Gain-Bandwidth product and Slew Rate with modulator performances (SNR, SNDR). Taking into account capacitive effects, a high degree of accuracy is obtained which is verified by transistor...
This paper demonstrates a fully integrated tri-band LO generation system based a low phase noise 12 GHz sub-harmonic VCO and an injection locked frequency tripler (ILFT) as the signal source. The system generates simultaneously three outputs at ƒ0, ƒ0/2 and 2׃0, with maximum frequency of 36 GHz, 18 GHz and 72 GHz respectively. The system which is implemented in a 0.25-µm SiGe:C BiCMOS technology,...
A signal generation system composed by a subhar-monic VCO followed by an injection-locked frequency tripler (ILFT) is designed in a 0.25 μm BiCMOS SiGe:C technology. The ILFT implements a cascoded current-biased common emitter configuration that exploits the second harmonic of the VCO to enhance the efficiency in the generation of the injecting signal responsible for the ILFT locking. At 30.8GHz,...
A 79GHz receiver front-end for automotive applications has been implemented in a 130nm SiGe technology supporting millimeter wave design. The receiver consists of a two-stage LNA, a double-balanced down-conversion Mixer and a synchronized VCO. Design and test results for each RF circuit block are presented, followed by a characterization of the integrated receiver.
This work reports on the implementation of a 2.4 GHz ultra low power (ULP) low noise amplifier (LNA) in a standard CMOS 0.13 µm process. The proposed design methodology consists in optimizing the tradeoff between RF performances and current consumption of the MOS transistor. The supply of the circuit controlled by a 3bits DAC varies from 0.4 to 0.6 V. This digital tuning allows maximizing the figure...
A novel technique for the stabilization of local oscillators is presented in this paper based on the combination of a Phase Locked Loop (PLL) and Delay Locked Loop (DLL) architecture. On one hand, phase noise performances are improved taking advantage of the both architecture and more particular to the non-accumulation of random timing jitter. On the other hand, such a methodology could relax constraints...
This paper presents the behavioral modeling and circuit design of an accurate multi-bit DAC dedicated to high-speed Continuous-time ΔΣ converters. The multi-bit DAC element mismatch is modeled, demonstrating that the non-linearities coming from the feedback DACs is awful for Continuous-time ΔΣ modulators. The proposed DAC is dimensioned in order to achieve best matching, reaching an unit current source...
This paper presents a novel method for analyzing the analog specifications of bandpass sampling (BPS) receivers. The method guarantees fast convergence to the required performance and can be exploited to study the best configurations for a given constraint (eg. power, integration) using different noise degradation distributions. A wide-band system-level simulation tool which separately models each...
In order to implement a built-in self-test (BIST) strategy for a radio frequency (RF) LC-voltage controlled oscillator (VCO) devoted to WiMax applications, an exhaustive study of the fault coverage achievable for this block is carried out. The peak-to-peak value of the output voltage is shown to be the best quantity to monitor. Once the fault is detected, it is shown that the BIST can be exploited...
A new differential LNA dedicated to 60 GHz band has been implemented in a 130 nm BiCMOS technology intended for millimeter-waves (mm-Waves) applications. Focusing on the circuit implementation which is a critical design step in mm-Waves range, this work proposes a systematic modeling of layout parasitic elements leading to almost perfectly fit measurement and simulation results. The two stage cascode...
This paper presents an original topology for Voltage Controlled Delay Element used in a DLL-based oscillator. This cell works from 1 to 10GHz achieving the phase noise performances required for the targeted wireless standards. The current consumption is lower than 9mA under 1V supply voltage. Thanks to the new topology a delay bank control scheme is feasible, paving the way to digitally controlled...
A fully integrated 23 GHz CMOS PLL-based synthesizer is presented. This circuit combines push-push oscillator with a latch based divider to achieve low-power dissipation and a small die. The circuit was designed in 130 nm bulk CMOS process from STMicroelectronics. The synthesized range is from 22 GHz up to 24.2 GHz, the power dissipation is 58 mW under 1.0 V power supply. The measured phase noise...
This paper deals with general discussion over high-speed data converter architectures. Nowadays, more and more researches are focused on the ability to design transceivers able to manage digital data as soon as possible right behind the antenna. These so-called Software Defined Radio architectures are one of the easiest ways to design a receiver with low time-to-market impact. Furthermore, most of...
To comply with the low power low voltage design constrains in modern RF CMOS technologies, a new LNA topology is here proposed. Implemented in a standard 130 nm CMOS technology, two circuits operating under a 1.4 V nominal voltage are reported. The first one dedicated to lower band of European UWB allocation -i.e. 3-5 GHz- achieves a 13.8 dB maximum gain for a 5.8 mA current consumption. NF is so...
A temperature and supply voltage independent voltage reference is presented. The design is carried out using the STM 65 nm CMOS process. An analytical study is carried out to show the feasibility to adjust the temperature independent output voltage controlling the biasing of the bulk of one transistor. A feedback is introduced in order to do so. Post-layout simulations confirm the analytical results...
mm-waves building block design is the meeting point of distributed and RF analog techniques. After reviewing the skills of a 130 nm mm-Wave dedicated back-end BiCMOS technology, this paper investigates these two design methodologies in an 80 GHz cascode differential LNA implementation. A third version of the circuit taking advantage of both approaches is finally proposed. Operating under 2.5 V and...
This paper explores new capabilities brought on by Independently Driven Double Gate CMOS transistors (IDGMOS) for analog baseband design. Since the gates are disconnected, the corresponding channels are coupled resulting in a dynamic threshold voltage tuning. This operation mode is exploited to create new analog functions and low-voltage circuits. A current mirror is redesigned using IDGMOS and it...
A resistive current reuse UWB LNA implemented in a 130 nm CMOS technology is here reported. Covering a 2 to 9 GHz band, the circuit provides an 11.5 dB gain for a 4.45 dB minimum noise figure. Across the frequency band of interest, the NF is kept below 9 dB. The broadband behaviour of the input stage allows achieving a very wide input matching. As well S11 is lower than -12 dB from 1 to 14.8 GHz while...
A resistive current reuse UWB LNA implemented in a 130 nm CMOS technology is here reported. Covering a 2 to 9 GHz band, the circuit provides an 11.5 dB gain for a 4.45 dB minimum noise figure. Across the frequency band of interest, the NF is kept below 9 dB. The broadband behaviour of the input stage allows achieving a very wide input matching. As well S11 is lower than -12 dB from 1 to 14.8GHz while...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.