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Video coding has become widespread through mobile devices. At the same time, the adopted resolutions have been enlarged, demanding more coding efficiency and motivating the development of the new state-of-the-art standard, High Efficiency Video Coding (HEVC). However, to achieve the required efficiency the new standard greatly increased the computational intensity. That, allied to real-time constraints...
The increasing resolutions combined with storage and processing limitations of mobile devices point to the need for new compression techniques for video coding. Meanwhile, to achieve higher compression rates without compromising quality, the coding process becomes more and more complex. In reference software of HEVC the most time consuming step is the execution of Motion Estimation (ME), which is...
The Sum of Absolute Transformed Differences (SATD) computation is one of the most time consuming functions of the High Efficiency Video Codec (HEVC) reference model (HM). Thus, dedicated hardware architectures are demanded for such metric. In HM, the SATDs are computed using the Hadamard Transform (HT) 8×8 or 4×4. When the partition sizes are larger than those two HT sizes listed, the SATD is computed...
The efficiency improvements achieved by new video coding standards come at the cost of a huge increase in the encoder computational complexity. Paradoxically, such increasing complexity is commonly addressed by methods that have an adverse effect on coding efficiency. In this work, we propose a method to reduce the complexity of HEVC Hadamard ME, without compromising coding efficiency. Our method...
State-of-the-art video coding standards adopt large block and transform sizes. Moreover, as resolutions keep growing, there is a trend in adopting even larger structures in future video encoders, resulting in higher complexity. Therefore, the design of energy-efficient architectures for variable block size distortion metrics are key to keep the energy requirements of battery devices under a reasonable...
The main reason for the long time and high energy requirements of state-of-the-art Video Coding (VC) standards, such as the HEVC, is the large amount of distortion calculations. Among the most known and used ones is the Sum of Squared Differences (SSD) which has a strong correlation with the Peak Signal-to-Noise Ratio (PSNR). Such correlation is explored by current encoders to provide a good trade-off...
The most energy-hungry step of Video Coding (VC) is the Block Matching Algorithm (BMA), even when a simple similarity metric such as the Sum of Absolute Differences (SAD) is employed. Moreover, with the increasing resolutions supported by state-of-the-art VC standards (H.264/AVC, HEVC and VP9), the SAD must be as energy-efficient as possible to increase the battery lifetime in portable mobile devices...
In recent years, energy efficiency became a concern for video coding as battery powered devices incorporate more and more multimedia applications. Moreover, the increased number of pixels arising in high definition video opens new opportunities to trade-off between quality and energy. Originally devised to increase throughput, pixel subsampling, also known as pel decimation, can be applied in block...
This work investigates the trade-offs between energy and quality in video coding when pel decimation is applied. Realistic estimates for area and energy per block were obtained by simulating five different architectures specially designed to compute the Sum of Absolute Differences (SAD) for 4×4 pixel blocks. Among these architectures, one can be configured to operate with 1:1, 4:3, 2:1 or 4:1 sample...
In this paper we present energy-efficient Hadamard-based Sum of Absolute Transformed Differences (SATD) architectures. We relied on two state of the art methods for SATD, one using the Fast Hadamard Transform (FHT) butterfly and another one using the so-called Transform-Exempted (TE) SATD algorithm. Those were combined with architectural decisions, as the use of a transpose buffer. A total of six...
As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. This paper presents a VLSI architecture that can be configured to compute the SAD of 4×4 pixel blocks with no subsampling or with 2:1 or 4:1 subsampling (pel decimation)...
Although pel decimation has been widely used to reduce the computational effort in video coding, there is no consensus about the optimal subsampling pattern. This paper presents an extensive analytical and statistical comparison of several different subsampling patterns using analysis of variance. The investigation includes commonly used patterns as well as seven proposed ones. The experiments were...
This paper presents a new configurable VLSI architecture for Sum of Absolutes Differences (SAD) calculation with pel decimation capabilities. It was also described a non-configurable architecture for comparison. The proposed SAD architecture as well as a non-configurable architecture were synthesized to both nominal and Low-Vdd/High-Vt versions of a commercial 90nm technology. Synthesis results demonstrated...
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