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List decoding is a promising technique for machine type communications (MTC) and other applications that pursue the high-coding gain of convolutional codes. However, there are obstacles that degrade the availability of list decoding. In specific, non-tail-biting list decoding involves high demands of data storage, while tail-biting list decoding requires substantial computational resources to preserve...
The latest extended-coverage (EC-GSM-IoT) and high-throughput (EGPRS2A) enhancements make GSM competitive to LTE-based cIoT standards such as NB-IoT with the advantage of global coverage today. This work introduces the first fully-integrated RF-SoC supporting the complete GSM standard family ranging from EC-GSM-IoT through EGPRS2A. The RF-SoC achieves −121.7 dBm receiver sensitivity and peak data...
Initial timing acquisition in narrow-band IoT (NB- IoT) devices is done by detecting a periodically transmitted known sequence. The detection has to be done at lowest possible latency, because the RF- transceiver, which dominates downlink power consumption of an NB-IoT modem, has to be turned on throughout this time. Auto-correlation detectors show low computational complexity from a signal processing...
It is almost always assumed that the algebraic structure underlying non-binary Low-Density Parity-Check (LDPC) codes are Finite Fields. However, when considering non-binary LDPC belief-propagation (BP) decoding, Finite Fields are actually over constrained. In this contribution, we discuss the minimal requirements of the algebraic structure used for non-binary LDPC decoding which we denote Finite Division...
Moore's law will slow down in the next decades and potentially even stop due to unbridgeable physical challenges. In order to continue the trend of progressively increasing complex designs with ever-decreasing costs per transistor, the CMOS technology will have to be replaced by a new device technology. There are a multitude of these technologies known today. However, the identification of the most...
Using hardware-accelerated HDL emulators of fixed-point implementations has several advantages in comparison to C-based simulations: The high degree of parallelism for example of field-programmable gate-array based hardware accelerators promise an increased emulation throughput. Furthermore, the HDL model of the considered circuit can be used in the following design process making an additional verification...
The challenge in designing LDPC decoders is the efficient realization of the global communication between the two basic component types of such a decoder. Tight timing constraints in high-performance applications demand for a dedicated interconnect, which in general negatively affects the decoder features, especially the silicon area. Various approaches to reduce this impact have been discussed in...
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