The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper describes a WiFi/BT combo SoC with integrated dual-band PAs, LNAs and T/R switches, supporting concurrent receiving for improved throughput by 30% in dense networking environment of 2.4GHz ISM band and wide-range transmitting capability (>20dB) while keeping good output power accuracy and PA power efficiency. The measured 2.4GHz/5GHz WiFi 54Mbps RX sensitivity is −78.2/−78.1dBm and Pout...
This paper describes a dual-band 802.11abgn/ac compliant transceiver in a 4-in-l combo connectivity SoC. It integrates the PAs, LNAs, T/R switches, and the 5GHz Balun. Due to the transmitter architecture and adaptive biasing scheme both are tailored for wide bandwidth, the 5GHz transmitter achieves 18.2dBm average output power for 802.11ac VHT80 MCS9 (Modulation and Coding Scheme 9). Within the 80MHz...
This paper describes a 55nm, 0.6mm2 Bluetooth SoC integrated in cellular baseband. Several techniques are used to enhance co-existence performance of Bluetooth with cellular and Wi-Fi. First is the design of current-mode interfaces from LNA to complex BPF for better linearity and the additional antialiasing LPF placed before ADC for outband rejection in the RX. Second is the use of a passive voltage...
A dual-band RF receiver front-end for DVB-H is presented in this paper. It includes two sets of single-ended input LNAs, respectively followed by a double-balanced current-driven passive mixer with a low impedance load. The receiver front-end is implemented in a 1P6M 65 nm CMOS process and occupies a total chip area of 2.17 mm2. It exhibits a conversion gain of 36.5 dB, an IIP3 of -13.1 dBm, an IIP2...
A fully integrated direct-conversion tuner is implemented in 0.13 mum CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.