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Physical design tools must handle huge amounts of data in order to solve problems for circuits with millions of cells. Traditionally, Electronic Design Automation tools are implemented using Object-Oriented Design. However, using this paradigm may lead to overly complex objects that result in waste of cache memory space. This memory wasting harms cache locality exploration and, consequently, degrades...
During physical synthesis, global placement produces a solution where cells are overlapped or misaligned with respect to circuit sites and rows. Therefore, a legalization step relocates a subset of cells in order to satisfy a set of legality constraints. Although several techniques have been proposed to solve the legalization problem, they were designed without considering parallelization. This work...
During physical synthesis, global placement and incremental optimization steps such as gate sizing, buffer insertion and timing-driven placement, produce placements where cells are overlapped or misaligned with respect to sites and rows predefined in the used standard cell library. Therefore, a legalization procedure must be used to keep the placement legality. In the case of incremental optimization...
Circuit legalization removes overlaps and keeps cell alignment with power rails whileminimizing total cell displacement. Legalization is applied not only after global placement, but also after incremental optimization steps like detailed placement, gate sizing, and buffer insertion. Applying full legalization after such incremental optimizations is too time-consuming. That is why physical synthesis...
The increasing impact of interconnections on the overall circuit performance renders physical design a crucial step to timing closure. Several techniques are used to optimize timing within the flow, such as gate sizing, buffer insertion, and timing-driven placement (TDP). Unfortunately, gate sizing and buffer insertion are not capable of modifying the length of interconnections. Although TDP is able...
This paper presents VLSI architectures to perform Digital Modulation Classification based on Support Vector Machines. In order to obtain suitably small circuitry, the designed architectures use a recently proposed front end that is based on histograms. Four versions of classifier architectures were modeled in Verilog and synthesized for a 90 nm commercial standard cells library, two of them using...
This paper presents a Radix-2 Single-Path Delay Feedback (R2SDF) configurable processor to calculate 64/128/512/1024/2048-point Fast Fourier Transform (FFT). Such range of FFT input sequences allows for the realization of the widely used wireless protocols IEEE 802.11n (WLAN) and the IEEE 802.16 (WiMax). The presented R2SDF configurable processor, as well as a fully sequential configurable processor...
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