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Physical design tools must handle huge amounts of data in order to solve problems for circuits with millions of cells. Traditionally, Electronic Design Automation tools are implemented using Object-Oriented Design. However, using this paradigm may lead to overly complex objects that result in waste of cache memory space. This memory wasting harms cache locality exploration and, consequently, degrades...
Modern technologies provide wide and thick metal layers that must be wisely used to reduce the delay of critical interconnections. After global routing, incremental layer assignment can improve the circuit timing by properly selecting critical interconnect segments to be routed in the faster (but very limited) wires on upper layers. Existing techniques based on net-by-net iterative improvement may...
As VLSI technology scales to deep sub-micron, design for interconnections becomes increasingly challenging. The traditional bus routing follows a sequential bit-by-bit order, and few works explicitly target inter-bit regularity for signal groups via multi-layer topology selection. To overcome these limitations, we present Streak, an efficient framework that combines topology generation and wire synthesis...
In advanced technology nodes, standard cell pin access is becoming challenging due to a small number of routing tracks and complex design-for-manufacturing constraints. Pin access interference is further exacerbated by unidirectional routing, which is highly preferred to enable high-density metal patterns and comply with self-aligned multiple patterning solutions. Previous manufacturing-aware routing...
During physical synthesis, global placement produces a solution where cells are overlapped or misaligned with respect to circuit sites and rows. Therefore, a legalization step relocates a subset of cells in order to satisfy a set of legality constraints. Although several techniques have been proposed to solve the legalization problem, they were designed without considering parallelization. This work...
During physical synthesis, global placement and incremental optimization steps such as gate sizing, buffer insertion and timing-driven placement, produce placements where cells are overlapped or misaligned with respect to sites and rows predefined in the used standard cell library. Therefore, a legalization procedure must be used to keep the placement legality. In the case of incremental optimization...
Circuit legalization removes overlaps and keeps cell alignment with power rails whileminimizing total cell displacement. Legalization is applied not only after global placement, but also after incremental optimization steps like detailed placement, gate sizing, and buffer insertion. Applying full legalization after such incremental optimizations is too time-consuming. That is why physical synthesis...
The increasing impact of interconnections on the overall circuit performance renders physical design a crucial step to timing closure. Several techniques are used to optimize timing within the flow, such as gate sizing, buffer insertion, and timing-driven placement (TDP). Unfortunately, gate sizing and buffer insertion are not capable of modifying the length of interconnections. Although TDP is able...
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