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Downsizing the Cu signal traces in the redistribution layer is an effective approach to increasing the number of signal I/O lines and thereby greatly increasing signal processing performance between logic and memory chips in advanced fine-pitch packaging. Downsized Cu traces, however, are vulnerable to current stress, which degrades electromigration resistance. This is a serious problem in advanced...
Aggressive scaling down of the Cu trace pitch in the redistribution layer (RDL) is needed to meet the design rule for high-density I/O used in advanced packaging. Such a downsized RDL, however, will be vulnerable to voltage and current stresses, in addition to environmental stress. Voltage stress, for example, degrades the reliability of electrical isolation (dielectric strength). This will likely...
An enhanced redistribution layer architecture has been developed in which the Cu wires are directly covered with a double layer consisting of two types of dielectrics by using a semi-additive process. The double layer enhanced the thermal and electrical reliabilities of the Cu wires. Moreover, it enabled fabrication of a single-sided nine-level redistribution layer embedded with a fully stacked via...
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